cvw/fpga/constraints/marked_debug.txt
2023-07-31 14:13:09 -05:00

8 lines
318 B
Plaintext

wally/wallypipelinedcore.sv: logic PCM
wally/wallypipelinedcore.sv: logic TrapM
wally/wallypipelinedcore.sv: logic InstrValidM
wally/wallypipelinedcore.sv: logic InstrM
lsu/lsu.sv: logic LSUHADDR
lsu/lsu.sv: logic LSUHREADY
lsu/lsu.sv: logic LSUHWDATA