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103 lines
4.0 KiB
Systemverilog
103 lines
4.0 KiB
Systemverilog
///////////////////////////////////////////
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// wally-pipelinedsoc.sv
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//
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// Written: David_Harris@hmc.edu 6 November 2020
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// Modified:
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//
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// Purpose: System on chip including pipelined processor and memories
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// Full RV32/64IC instruction set
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//
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// Note: the CSRs do not support the following features
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//- Disabling portions of the instruction set with bits of the MISA register
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//- Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register
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// As of January 2020, virtual memory is not yet supported
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module wallypipelinedsoc (
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input logic clk, reset_ext,
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output logic reset,
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// AHB Lite Interface
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// inputs from external memory
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input logic [`AHBW-1:0] HRDATAEXT,
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input logic HREADYEXT, HRESPEXT,
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output logic HSELEXT,
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// outputs to external memory, shared with uncore memory
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output logic HCLK, HRESETn,
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output logic [31:0] HADDR,
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output logic [`AHBW-1:0] HWDATA,
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output logic HWRITE,
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output logic [2:0] HSIZE,
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output logic [2:0] HBURST,
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output logic [3:0] HPROT,
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output logic [1:0] HTRANS,
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output logic HMASTLOCK,
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output logic HREADY,
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// I/O Interface
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input logic TIMECLK,
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input logic [31:0] GPIOPinsIn,
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output logic [31:0] GPIOPinsOut, GPIOPinsEn,
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input logic UARTSin,
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output logic UARTSout,
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input logic SDCCmdIn,
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output logic SDCCmdOut,
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output logic SDCCmdOE,
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input logic [3:0] SDCDatIn,
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output logic SDCCLK
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);
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// Uncore signals
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// logic reset;
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logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore
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logic HRESP;
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logic TimerIntM, SwIntM; // from CLINT
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logic [63:0] MTIME_CLINT; // from CLINT to CSRs
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logic ExtIntM; // from PLIC
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logic [2:0] HADDRD;
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logic [3:0] HSIZED;
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logic HWRITED;
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// synchronize reset to SOC clock domain
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synchronizer resetsync(.clk, .d(reset_ext), .q(reset));
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// instantiate processor and memories
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wallypipelinedcore core(.clk, .reset,
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.TimerIntM, .ExtIntM, .SwIntM,
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.MTIME_CLINT,
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.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA,
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.HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
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.HADDRD, .HSIZED, .HWRITED
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);
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uncore uncore(.HCLK, .HRESETn, .TIMECLK,
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.HADDR, .HWDATAIN(HWDATA), .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
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.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED,
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.TimerIntM, .SwIntM, .ExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT,
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.HSELEXT,
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.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK
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);
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endmodule
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