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48 lines
2.1 KiB
Systemverilog
48 lines
2.1 KiB
Systemverilog
///////////////////////////////////////////
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// dcu.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Data cache unit
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// Top level of the memory-stage hart logic
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// Contains data cache, subword read/write datapath, interface to external bus
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module dcu (
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input logic [1:0] MemRWM,
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input logic [`XLEN-1:0] ReadDataM,
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input logic [`XLEN-1:0] DataAdrM,
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input logic [2:0] Funct3M,
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output logic [`XLEN-1:0] ReadDataExtM,
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input logic [`XLEN-1:0] WriteDataFullM,
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output logic [`XLEN-1:0] WriteDataM,
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output logic [7:0] ByteMaskM,
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input logic DataAccessFaultM,
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output logic LoadMisalignedFaultM, LoadAccessFaultM,
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output logic StoreMisalignedFaultM, StoreAccessFaultM
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);
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memdp memdp(.*);
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endmodule
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