Ross Thompson 0377d3b2c9 Progress.		2021-06-24 13:05:22 -05:00
..
cache	Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.	2021-06-23 15:13:56 -05:00
ebu	Progress.	2021-06-24 13:05:22 -05:00
fpu	rv64f FLW passes imperas tests	2021-06-22 16:36:16 -04:00
generic	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
hazard	Progress.	2021-06-24 13:05:22 -05:00
ieu	Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.	2021-06-23 16:43:22 -05:00
ifu	Progress.	2021-06-24 13:05:22 -05:00
lsu	Progress.	2021-06-24 13:05:22 -05:00
mmu	added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day.	2021-06-23 19:59:06 -04:00
muldiv	Fixed lint WIDTH errors	2021-06-09 20:58:20 -04:00
privileged	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
uncore	Refactored pmachecker to have adrdecs used in uncore	2021-06-23 01:41:00 -04:00
wally	Progress.	2021-06-24 13:05:22 -05:00