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https://github.com/openhwgroup/cvw
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159 lines
2.7 KiB
ArmAsm
159 lines
2.7 KiB
ArmAsm
// pmppriority test cases
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// Kevin Wan kewan@hmc.edu 4/27/2023
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// want memory ranges to match:
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// 1. only the most significant address and none of the lower ones,
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// 2. the most significant address and ANY of the lower ones.
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#include "WALLY-init-lib.h"
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main:
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li t1, 0x21FFFFFF // start at 0x8000000 with a range of 1000000. Address format is set to NAPOT in pmpcfg.
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csrw pmpaddr0, t1
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csrw pmpaddr1, t1
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csrw pmpaddr2, t1
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csrw pmpaddr3, t1
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csrw pmpaddr4, t1
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csrw pmpaddr5, t1
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csrw pmpaddr6, t1
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csrw pmpaddr7, t1
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csrw pmpaddr8, t1
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csrw pmpaddr9, t1
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csrw pmpaddr10, t1
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csrw pmpaddr11, t1
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csrw pmpaddr12, t1
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csrw pmpaddr13, t1
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csrw pmpaddr14, t1
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csrw pmpaddr15, t1
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li t0, 0x1F
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csrw pmpcfg0, t0 //set to XWR and NAPOT
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sw zero, 0(sp)
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li t0, 0x1F00
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csrw pmpcfg0, t0
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sw zero, 0(sp)
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li t0, 0x1F1F
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csrw pmpcfg0, t0
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sw zero, 0(sp)
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li t0, 0x1F0000
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csrw pmpcfg0, t0
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sw zero, 0(sp)
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li t0, 0x1F1F1F
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csrw pmpcfg0, t0
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sw zero, 0(sp)
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li t0, 0x1F000000
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csrw pmpcfg0, t0
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sw zero, 0(sp)
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li t0, 0x1F1F1F1F
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csrw pmpcfg0, t0
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sw zero, 0(sp)
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li t0, 0x1F00000000
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csrw pmpcfg0, t0
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sw zero, 0(sp)
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li t0, 0x1F1F1F1F1F
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csrw pmpcfg0, t0
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sw zero, 0(sp)
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li t0, 0x1F0000000000
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csrw pmpcfg0, t0
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sw zero, 0(sp)
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li t0, 0x1F1F1F1F1F1F
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csrw pmpcfg0, t0
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sw zero, 0(sp)
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li t0, 0x1F000000000000
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csrw pmpcfg0, t0
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sw zero, 0(sp)
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li t0, 0x1F1F1F1F1F1F1F
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csrw pmpcfg0, t0
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sw zero, 0(sp)
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li t0, 0x1F00000000000000
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csrw pmpcfg0, t0
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sw zero, 0(sp)
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li t0, 0x1F1F1F1F1F1F1F1F
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csrw pmpcfg0, t0
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sw zero, 0(sp)
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li t0, 0x0
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csrw pmpcfg0, t0
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li t0, 0x1F
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csrw pmpcfg2, t0
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sw zero, 0(sp)
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li t0, 0x1F00
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csrw pmpcfg2, t0
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sw zero, 0(sp)
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li t0, 0x1F0000
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csrw pmpcfg2, t0
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sw zero, 0(sp)
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li t0, 0x1F00000000
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csrw pmpcfg2, t0
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sw zero, 0(sp)
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li t0, 0x1F0000000000
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csrw pmpcfg2, t0
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sw zero, 0(sp)
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li t0, 0x1F000000000000
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csrw pmpcfg2, t0
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sw zero, 0(sp)
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li t0, 0x1F00000000000000
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csrw pmpcfg2, t0
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sw zero, 0(sp)
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li t0, 0x1F1F1F1F1F1F1F1F
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csrw pmpcfg0, t0
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li t0, 0x1F
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csrw pmpcfg2, t0
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sw zero, 0(sp)
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li t0, 0x1F1F
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csrw pmpcfg2, t0
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sw zero, 0(sp)
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li t0, 0x1F1F1F
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csrw pmpcfg2, t0
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sw zero, 0(sp)
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li t0, 0x1F1F1F1F
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csrw pmpcfg2, t0
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sw zero, 0(sp)
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li t0, 0x1F1F1F1F1F
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csrw pmpcfg2, t0
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sw zero, 0(sp)
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li t0, 0x1F1F1F1F1F1F
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csrw pmpcfg2, t0
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sw zero, 0(sp)
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li t0, 0x1F1F1F1F1F1F1F
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csrw pmpcfg2, t0
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sw zero, 0(sp)
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li t0, 0x1F1F1F1F1F1F1F1F
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csrw pmpcfg2, t0
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sw zero, 0(sp)
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j done
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