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cvw/addins
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Jordan Carlin 1465a9f39f
Actually update riscv-arch-test
2024-09-23 22:08:11 -07:00
..
ahbsdc@33418c8dc1 Replaced the git@github with hptts:github submodule for ahbsdc which I hope will fix Lee's clone issue 2023-12-11 14:12:38 -06:00
berkeley-softfloat-3@3b70b5d814 Add softfloat as submodule 2024-09-15 00:20:39 -07:00
berkeley-testfloat-3@03c13d21db Switch to using testfloat submodule 2024-09-15 00:37:04 -07:00
branch-predictor-simulator@3e424e902f Swap in branch predictor simulator handling compressed instruction offsets 2023-11-21 16:42:41 -08:00
coremark@f3e8f2e094
cvw-arch-verif@80cdee231f Updated cvw-arch-verif 2024-09-05 16:41:58 -07:00
embench-iot@54fd9a0f10 repo cleanup and start to add CMO tests 2023-11-20 23:41:36 -08:00
FreeRTOS-Kernel@17a46c252f
riscv-arch-test@ce04b49305 Actually update riscv-arch-test 2024-09-23 22:08:11 -07:00
riscv-dv@f0c570d112 /cad/mentor/questa_sim-2023.4/questasim is fixed, relative paths to design and testbench files are fixed, and RISCV-DV submodule is updated back to the latest commit on master branch 2024-04-26 15:55:39 -07:00
riscvISACOV@ac9fa2d386 Fixed a subtle questa sim bug with imperasDV. On some linux systems 2024-08-29 14:00:52 -07:00
verilog-ethernet@c180b22ed5 Updated verilog-ethernet to remove all verilator warnings or at least suppress them. 2024-07-24 10:13:03 -05:00
vivado-boards@e5f0728cd2 Added new submodule for digilent fpga boards. 2023-07-17 16:25:37 -05:00
README.md Added some documenation about sparse-checkout for verilog-ethernet submodule. 2024-07-19 13:11:48 -05:00
sparse-checkout Cleanup in prep to merge the rvvi branch into main. 2024-07-19 15:48:20 -05:00

README.md

verilog-ethernet contains many ethernet devices. Wally's synthesizable RVVI interface only requires a small subset of these files. To do a sparse checkout of this repo copy sparse-checkout to cvw/.git/modules/addins/verilog-ethernet/info This will make the working directory only contain the necessary files.