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007812dbdc
The StallW from the hazard unit controls this. Previously it was in the dcache and controlled by both the HPTW and hazard unit. This caused an issue when the CPU expected the data to stay constant while stalled, but the HPTW was causing the data to be modified.
104 lines
3.9 KiB
Systemverilog
104 lines
3.9 KiB
Systemverilog
///////////////////////////////////////////
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// ieu.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Integer Execution Unit: datapath and controller
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module ieu (
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input logic clk, reset,
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// Decode Stage interface
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input logic [31:0] InstrD,
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input logic IllegalIEUInstrFaultD,
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output logic IllegalBaseInstrFaultD,
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output logic RegWriteD,
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// Execute Stage interface
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input logic [`XLEN-1:0] PCE,
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input logic [`XLEN-1:0] PCLinkE,
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input logic FWriteIntE,
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input logic IllegalFPUInstrE,
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input logic [`XLEN-1:0] FWriteDataE,
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output logic [`XLEN-1:0] PCTargetE,
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output logic MulDivE, W64E,
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output logic [2:0] Funct3E,
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output logic [`XLEN-1:0] SrcAE, SrcBE,
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output logic [4:0] RdE,
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input logic FWriteIntM,
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// Memory stage interface
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input logic DataMisalignedM, // from LSU
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input logic SquashSCW, // from LSU
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output logic [1:0] MemRWE, // read/write control goes to LSU
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output logic [1:0] MemRWM, // read/write control goes to LSU
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output logic [1:0] AtomicE, // atomic control goes to LSU
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output logic [1:0] AtomicM, // atomic control goes to LSU
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output logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM, // Address and write data to LSU
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output logic [2:0] Funct3M, // size and signedness to LSU
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output logic [`XLEN-1:0] SrcAM, // to privilege and fpu
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output logic [4:0] RdM,
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input logic DataAccessFaultM,
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input logic [`XLEN-1:0] FIntResM,
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// Writeback stage
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input logic [`XLEN-1:0] CSRReadValW, ReadDataM, MulDivResultW,
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input logic FWriteIntW,
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output logic [4:0] RdW,
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output logic [`XLEN-1:0] ReadDataW,
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// input logic [`XLEN-1:0] PCLinkW,
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output logic InstrValidM,
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// hazards
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input logic StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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output logic FPUStallD, LoadStallD, MulDivStallD, CSRRdStallD,
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output logic PCSrcE,
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input logic DivDoneE,
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input logic DivBusyE,
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output logic CSRReadM, CSRWriteM, PrivilegedM,
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output logic CSRWritePendingDEM,
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output logic StoreStallD
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);
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logic [2:0] ImmSrcD;
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logic [2:0] FlagsE;
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logic [4:0] ALUControlE;
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logic ALUSrcAE, ALUSrcBE;
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logic [2:0] ResultSrcW;
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logic TargetSrcE;
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logic SCE;
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logic InstrValidW;
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// forwarding signals
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logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E;
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logic [1:0] ForwardAE, ForwardBE;
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logic RegWriteM, RegWriteW;
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logic MemReadE, CSRReadE;
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logic JumpE;
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controller c(.*);
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datapath dp(.*);
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forward fw(.*);
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endmodule
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