Ross Thompson 007812dbdc Moved the ReadDataW register into the datapath. ... The StallW from the hazard unit controls this. Previously it was in the dcache and controlled by both the HPTW and hazard unit. This caused an issue when the CPU expected the data to stay constant while stalled, but the HPTW was causing the data to be modified.		2021-07-22 14:52:03 -05:00
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cache-sram.sv	A few more cache fixes	2021-04-13 01:07:40 -04:00
cacheLRU.sv	Tested all numbers of ways for dcache 1, 2, 4, and 8.	2021-07-22 10:38:07 -05:00
dcache.sv	Moved the ReadDataW register into the datapath.	2021-07-22 14:52:03 -05:00
DCacheMem.sv	Progress towards the test bench flush.	2021-07-12 14:22:13 -05:00
dmapped.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
icache.sv	Parameterized I$/D$ configurations and added sanity check assertions in testbench	2021-07-20 08:57:13 -04:00
ICacheCntrl.sv	Cleaned up icache and dcache.	2021-07-22 11:06:44 -05:00
ICacheMem.sv	Partial implementation of the data cache. Missing the fsm.	2021-07-07 17:52:16 -05:00
sram1rw.sv	change sram1rw to have a small delay so that we don't have signals changing on clock edges	2021-07-19 11:30:07 -04:00