cvw/pipelined/regression
2022-11-13 21:36:12 -06:00
..
slack-notifier
wave-dos
wkdir
buildrootBugFinder.py
fpga-wave.do Changed names of cache signals. 2022-11-13 21:36:12 -06:00
lint-wally
linux-wave.do Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks. 2022-10-23 13:46:50 -05:00
make-tests.sh
Makefile
makefile-memfile
regression-wally Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU 2022-10-10 10:22:12 -07:00
sim-buildroot
sim-buildroot-batch
sim-testfloat
sim-testfloat-batch
sim-wally
sim-wally-batch
testfloat.do
wally-harvard.do
wally-pipelined-batch.do Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults. 2022-10-11 10:47:13 -05:00
wally-pipelined.do Sort of solved the bit width warning for dtim, irom ranges. 2022-10-19 10:42:19 -05:00
wave-all.do
wave-fpu.do Removed unused FPU waves 2022-10-14 17:33:32 -07:00
wave.do Changed names of cache signals. 2022-11-13 21:36:12 -06:00