amaiuolo 000117fcd4 added amaiuolo@hmc.edu		2022-10-13 22:36:52 +00:00
..
cache	Possible fix to the bus cache interaction.	2022-09-27 11:34:33 -05:00
ebu	Added logic to not implement the save/restore muxes for LSU in the EBU's controller input stage.	2022-09-29 18:37:34 -05:00
fpu	added amaiuolo@hmc.edu	2022-10-13 22:36:52 +00:00
generic	changed always_ff to always in sram1p1rw to fix testbench complaint	2022-09-25 19:56:40 -07:00
hazard	Added comments about planned changes.	2022-08-29 09:48:00 -05:00
ieu	Eliminated store after store stall when no cache; simplified divshiftcalc logic.	2022-09-21 13:02:34 -07:00
ifu	Disable IFU bus access on TrapM.	2022-10-01 14:54:16 -05:00
lsu	Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.	2022-09-28 17:39:51 -05:00
mmu	Created two new pma regions for dtim and irom.	2022-08-28 13:50:50 -05:00
muldiv	Clean up unused signals	2022-05-12 14:49:58 +00:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.	2022-09-28 17:39:51 -05:00
uncore	Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore.	2022-09-29 11:54:03 -05:00
wally	Added integer inputs and flags to divsqrt	2022-09-29 23:08:27 +00:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00