mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 04:54:29 +00:00
264 lines
8.9 KiB
YAML
264 lines
8.9 KiB
YAML
trek:
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platform_config:
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doc: >-
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Testbench platform specific configuration.
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processors:
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doc: >-
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Information about available processors.
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processor_count:
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value: 1
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doc: >-
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How many processors can be used by the generated test case
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sw_threads_per_processor:
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value: 2
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doc: >-
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How many software threads to put on each processor
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tlm_generic_ports:
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doc: >-
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Information about available tlm_generic_payload ports
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port_count:
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value: 0
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doc: >-
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How many tlm ports to use for memory operations
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threads_per_port:
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value: 4
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doc: >-
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How many threads to put on each tlm port
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debug:
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value: 1
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doc: >-
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Turn on for verbose tlm port messages
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memories:
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doc: >-
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Information about memory regions that can be used by the generated test case.
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defaults:
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doc: >-
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Default values for all memories
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natural_alignment:
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value: 1
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doc: >-
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Should all memory addresses be naturally aligned (up to 8 byte alignment)
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init_type:
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value: frontdoor
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doc: >-
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Strategy to use for memory initialization.
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Options are:
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- static
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- backdoor
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- frontdoor
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memory:
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doc: >-
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Define a memory region.
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Multiple memory regions may be defined in this section.
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name:
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value: ddr0
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doc: >-
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Name of the memory region
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base:
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value: 0x83000000
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doc: >-
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Base address of memory region.
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Ignored for `static` initialized memory
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size:
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value: 0x100000
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doc: >-
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Size of memory region in bytes.
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init_type:
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value: backdoor #frontdoor
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doc: >-
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Strategy to use for memory initialization.
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Options are:
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- static
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- backdoor
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- frontdoor
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caches:
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doc: >-
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parameters related to cache architecture
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cache_line_size:
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value: 64
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doc: >-
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Size of a cache line in bytes
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llc_cache_size:
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value: 0x200000
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doc: >-
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size of last level cache in bytes
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llc_cache_ways:
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value: 8
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doc: >-
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number of ways in the last level cache
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mailbox:
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doc: >-
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Configure memory mailbox usage
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type:
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value: single
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doc: >-
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Configure mailbox type.
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Options are:
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- single: for use by TrekBox with backdoor access
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- queue: for use in post-silicon post-process flow
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single:
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doc: >-
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Detail settings when mailbox type is `single`
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init_type:
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value: backdoor #static
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doc: >-
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Strategy to use for mailbox memory initialization.
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Options are:
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- static
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- backdoor
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- frontdoor
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c2t_base:
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value: 0x82000000
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doc: >-
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Fixed base address of C to trekbox mailbox region.
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Allow 64 bytes per processor.
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Used for init_type of `backdoor` and `frontdoor` only.
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t2c_base:
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value: 0x82001000
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doc: >-
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Fixed base address of trekbox to C mailbox region.
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Allow 64 bytes per processor.
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Used for init_type of `backdoor` and `frontdoor` only.
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cacheable:
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value: 1
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doc: >-
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Set this parameter to 1 to do a cache flush after every mailbox
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write.
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queue:
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doc: >-
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Detail settings when mailbox type is `queue`
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length:
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value: 1000
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doc: >-
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Max number of messages that can be stored in the queue mailbox.
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Longer tests may need a larger queue.
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debug:
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value: 0
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doc: >-
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If this flag is set to 1, messages will be printed directly to the
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console instead of being queued in memory.
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stdio:
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doc: >-
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Is the <stdio> standard library available for use by the generated test.
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available:
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value: 0
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doc: >-
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Set this value to 0 of the <stdio> library is not available in
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your system.
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use_lock:
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value: 1
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doc: >-
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Calls to <stdio> console print messages will be mutex locked unless
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this flag is set to 0.
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header:
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doc: >-
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Verbatim code that will be put into the header section of the test.
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value: |-
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declaration:
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doc: >-
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Verbatim code that will be put into the declaration section of the test.
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value: |-
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extern void tohost_exit(int status);
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#undef trek_exit
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#define trek_exit(status) tohost_exit(status);
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int main(void)
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{
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return trek_main();
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}
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mmu: # Trek can generate code to program page/translation tables
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# that you MAY want to use with your SDV generated C files.
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# Here, you have some control over that process.
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va_bits: 39 # How many bits are used for virtual addresses
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#
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# For aarch64, the value here is used to determine the
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# "initial lookup level" (as detailed in Table D5-13).
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# This must correlate to TCR_EL3.T0SZ!
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#
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# For riscv64, only 39, 48, and 57 are supported
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# corresponding to "Sv39", "Sv48", and "Sv57".
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#
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# default: 39 [from T0SZ=64-39=25(0x19)]
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memory_map: # A *MAP* of all memory regions, excluding the
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# memory_resources in your platformConfig.h file.
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#
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# Each map entry should be a unique name.
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#
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# Mandatory submap pairs:
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# normal: *true*/false (false = "device"/"io" memory)
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# begin: starting address
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# end: ending address
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#
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# Optional submap pairs:
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# readable: *true*/false
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# writeable: *true*/false
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# executable: true/*false*
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# cacheable: *true*/false (*false* for device)
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# share_type (aarch64 only): *inner-shareable*,
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# outer-shareable, non-shareable
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#
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# Note that memory_resources will use all defaults.
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#
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# Note that "normal: false" (device-memory) change defaults
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# to "cacheable = false", and on arch64 it implies
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# share_type = non-shareable, and alloc_type = no-allocate
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UART0:
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type: device
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begin: 0x10000000
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end: 0x10000fff
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code:
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type: normal
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begin: 0x80000000
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end: 0x807fffff
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executable: true
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stack:
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type: normal
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begin: 0x87000000
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end: 0x87ffffff
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aarch64: # Customizations that are only valid for aarch64.
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TCR_EL3: 0x80923519 # Should Trek to program the TCR_TL3 register? If
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# so, put the value here. If not, comment out
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# this option.
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# NOTE: T0SZ should correlate to va_bits above!
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# default: -no default-
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allocate_type: read-write-allocate # Default allocate_type.
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# read-allocate, write-allocate,
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# *read-write-allocate*, no-allocate
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cache_type: write-back-nontransient # non-cacheable,
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# write-through-transient,
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# write-back-transient,
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# write-through-non-transient,
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# *write-back-non-transient*
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device_type: nGnRnE # *nGnRnE*, nGnRE, nGRE, GRE
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share_type: inner-shareable # non-shareable
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# inner-shareable
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# outer-shareable
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riscv64: # Customizations that are only valid for riscv64.
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Svnapot: false # If standard extension "Svnapot" is implemented, and
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# when you are using Sv39, you might set this to "true"
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# to allow PTE bit[63] "N" to be set when appropriate.
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# default: false
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Svpbmt: true # If standard extension "Svpbmt" is implemented, and
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# when you are using Sv39, you might set this to "true"
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# to allow cacheable/device information to flow into
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# bits[62:61] "PBMT" as appropriate.
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# default: false
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