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https://github.com/openhwgroup/cvw
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171 lines
7.8 KiB
Systemverilog
Executable File
171 lines
7.8 KiB
Systemverilog
Executable File
///////////////////////////////////////////
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// fcmp.sv
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//
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// Written: me@KatherineParry.com
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// Modified: 7/5/2022
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//
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// Purpose: Floating-point comparison unit
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//
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// Documentation: RISC-V System on Chip Design
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// OpCtrl values
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// 110 min
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// 101 max
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// 010 equal
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// 001 less than
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// 011 less than or equal
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module fcmp import cvw::*; #(parameter cvw_t P) (
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input logic [P.FMTBITS-1:0] Fmt, // format of fp number
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input logic [2:0] OpCtrl, // see above table
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input logic Zfa, // Zfa variants: fminm, fmaxm, fleq, fltq
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input logic Xs, Ys, // input signs
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input logic [P.NE-1:0] Xe, Ye, // input exponents
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input logic [P.NF:0] Xm, Ym, // input mantissa
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input logic XZero, YZero, // is zero
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input logic XNaN, YNaN, // is NaN
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input logic XSNaN, YSNaN, // is signaling NaN
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input logic [P.FLEN-1:0] X, Y, // original inputs (before unpacker)
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output logic CmpNV, // invalid flag
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output logic [P.FLEN-1:0] CmpFpRes, // compare floating-point result
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output logic [P.XLEN-1:0] CmpIntRes // compare integer result
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);
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logic LTabs, LT, EQ; // is X < or > or = Y
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logic [P.FLEN-1:0] NaNRes; // NaN result
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logic BothZero; // are both inputs zero
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logic EitherNaN, EitherSNaN; // are either input a (signaling) NaN
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assign LTabs= {1'b0, Xe, Xm} < {1'b0, Ye, Ym}; // unsigned comparison, treating FP as integers
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assign LT = (Xs & ~Ys) | (Xs & Ys & ~LTabs & ~EQ) | (~Xs & ~Ys & LTabs); // signed comparison
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assign EQ = (X == Y);
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assign BothZero = XZero&YZero;
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assign EitherNaN = XNaN|YNaN;
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assign EitherSNaN = XSNaN|YSNaN;
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// flags
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// Min/Max - if an input is a signaling NaN set invalid flag
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// LT/LE - signaling - sets invalid if NaN input
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// EQ - quiet - sets invalid if signaling NaN input
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always_comb begin
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casez (OpCtrl[2:0])
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3'b110: CmpNV = EitherSNaN; //min
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3'b101: CmpNV = EitherSNaN; //max
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3'b010: CmpNV = EitherSNaN; //equal
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3'b0?1: if (P.ZFA_SUPPORTED)
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CmpNV = Zfa ? EitherSNaN : EitherNaN; // fltq,fleq / flt,fle perform CompareQuietLess / CompareSignalingLess differing on when to set invalid
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else CmpNV = EitherNaN; // flt, fle
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3'b100: CmpNV = 1'b0;
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default: CmpNV = 1'bx;
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endcase
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end
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// fmin/fmax of two NaNs returns a quiet NaN of the appropriate size
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// for IEEE, return the payload of X
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// for RISC-V, return the canonical NaN
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// select the NaN result
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if (P.FPSIZES == 1)
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if(P.IEEE754) assign NaNRes = {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]};
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else assign NaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
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else if (P.FPSIZES == 2)
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if(P.IEEE754) assign NaNRes = Fmt ? {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]} : {{P.FLEN-P.LEN1{1'b1}}, Xs, {P.NE1{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF1]};
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else assign NaNRes = Fmt ? {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}} : {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, (P.NF1-1)'(0)};
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else if (P.FPSIZES == 3)
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always_comb
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case (Fmt)
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P.FMT:
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if(P.IEEE754) NaNRes = {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]};
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else NaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
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P.FMT1:
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if(P.IEEE754) NaNRes = {{P.FLEN-P.LEN1{1'b1}}, Xs, {P.NE1{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF1]};
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else NaNRes = {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, (P.NF1-1)'(0)};
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P.FMT2:
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if(P.IEEE754) NaNRes = {{P.FLEN-P.LEN2{1'b1}}, Xs, {P.NE2{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF2]};
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else NaNRes = {{P.FLEN-P.LEN2{1'b1}}, 1'b0, {P.NE2{1'b1}}, 1'b1, (P.NF2-1)'(0)};
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default: NaNRes = {P.FLEN{1'bx}};
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endcase
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else if (P.FPSIZES == 4)
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always_comb
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case (Fmt)
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2'h3:
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if(P.IEEE754) NaNRes = {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]};
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else NaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
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2'h1:
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if(P.IEEE754) NaNRes = {{P.FLEN-P.D_LEN{1'b1}}, Xs, {P.D_NE{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.D_NF]};
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else NaNRes = {{P.FLEN-P.D_LEN{1'b1}}, 1'b0, {P.D_NE{1'b1}}, 1'b1, (P.D_NF-1)'(0)};
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2'h0:
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if(P.IEEE754) NaNRes = {{P.FLEN-P.S_LEN{1'b1}}, Xs, {P.S_NE{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.S_NF]};
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else NaNRes = {{P.FLEN-P.S_LEN{1'b1}}, 1'b0, {P.S_NE{1'b1}}, 1'b1, (P.S_NF-1)'(0)};
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2'h2:
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if(P.IEEE754) NaNRes = {{P.FLEN-P.H_LEN{1'b1}}, Xs, {P.H_NE{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.H_NF]};
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else NaNRes = {{P.FLEN-P.H_LEN{1'b1}}, 1'b0, {P.H_NE{1'b1}}, 1'b1, (P.H_NF-1)'(0)};
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endcase
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// Min/Max
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// - outputs the min/max of X and Y
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// - -0 < 0
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// - if both are NaN return quiet X
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// - if one is a NaN output the non-NaN
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always_comb
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if(OpCtrl[0]) // MAX
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if (Zfa & P.ZFA_SUPPORTED) // fmaxm perform IEEE754 maxNum that produce NaN if either input is NaN
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if (XNaN | YNaN) CmpFpRes = NaNRes; // either input is NaN
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else
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if (LT) CmpFpRes = Y; // X < Y
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else CmpFpRes = X; // X > Y
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else // fmax performs IEEE754 maxNumber that produces NaN if both inputs are NaN
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if(XNaN)
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if(YNaN) CmpFpRes = NaNRes; // X = NaN Y = NaN
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else CmpFpRes = Y; // X = NaN Y != NaN
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else
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if(YNaN) CmpFpRes = X; // X != NaN Y = NaN
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else // X,Y != NaN
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if(LT) CmpFpRes = Y; // X < Y
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else CmpFpRes = X; // X > Y
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else // MIN
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if (Zfa & P.ZFA_SUPPORTED) // fminm perform IEEE754 minNum that produce NaN if either input is NaN
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if (XNaN | YNaN) CmpFpRes = NaNRes; // either input is NaN
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else
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if (LT) CmpFpRes = X; // X < Y
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else CmpFpRes = Y; // X > Y
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else // fmin performs IEEE754 minNumber that produces NaN if both inputs are NaN
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if(XNaN)
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if(YNaN) CmpFpRes = NaNRes; // X = NaN Y = NaN
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else CmpFpRes = Y; // X = NaN Y != NaN
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else
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if(YNaN) CmpFpRes = X; // X != NaN Y = NaN
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else // X,Y != NaN
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if(LT) CmpFpRes = X; // X < Y
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else CmpFpRes = Y; // X > Y
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// LT/LE/EQ
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// - -0 = 0
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// - inf = inf and -inf = -inf
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// - return 0 if comparison with NaN (unordered)
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assign CmpIntRes = {(P.XLEN-1)'(0), (((EQ|BothZero)&OpCtrl[1])|(LT&OpCtrl[0]&~BothZero))&~EitherNaN};
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endmodule
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