#!/bin/bash
# check for warnings in Verilog code
# The verilator lint tool is faster and better than Questa so it is best to run this first.

export PATH=$PATH:/usr/local/bin/
verilator=`which verilator`

basepath=$(dirname $0)/..

if [ "$1" == "-nightly" ]; then
    configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i) # fdqh_rv64gc
    derivconfigs=`ls $WALLY/config/deriv`
    for entry in $derivconfigs
    do
        configs[${#configs[@]}]=$entry
    done
else
    configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc)
fi

for config in ${configs[@]}; do
    echo "$config linting..."
    if !($verilator --no-timing --lint-only --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
        echo "Exiting after $config lint due to errors or warnings"
        exit 1
    fi
done
echo "All lints run with no errors or warnings"

# --lint-only just runs lint rather than trying to compile and simulate
# -I points to the include directory where files such as `include config.vh  are found

# For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command
# Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist.