**/work*
**/wally_*.log

.nfs*

__pycache__/
.vscode/

#External repos
addins/riscv-arch-test/Makefile.include
addins/riscv-tests/target
addins/TestFloat-3e/build/Linux-x86_64-GCC/*
benchmarks/embench/wally*.json

#vsim work files to ignore
transcript
vsim.wlf
wlft*
wlft*
/imperas-riscv-tests/FunctionRadix_32.addr
/imperas-riscv-tests/FunctionRadix_64.addr
/imperas-riscv-tests/FunctionRadix.addr
/imperas-riscv-tests/ProgramMap.txt
/imperas-riscv-tests/logs
*.o
*.d
*.vstf
testsBP/*/*/*.elf*
testsBP/*/OBJ/*
testsBP/*/*.a
tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/*
tests/riscof/riscof_work/
tests/riscof/config32.ini
tests/riscof/config32e.ini
tests/riscof/config64.ini
tests/linux-testgen/linux-testvectors/*
!tests/linux-testgen/linux-testvectors/tvCopier.py
!tests/linux-testgen/linux-testvectors/tvLinker.sh
!tests/linux-testgen/linux-testvectors/tvUnlinker.sh
tests/linux-testgen/buildroot
tests/linux-testgen/buildroot-image-output
tests/linux-testgen/buildroot-config-src/main.config.old
tests/linux-testgen/buildroot-config-src/linux.config.old
tests/linux-testgen/buildroot-config-src/busybox.config.old
sim/slack-notifier/slack-webhook-url.txt
sim/logs
fpga/generator/IP
fpga/generator/vivado.*
fpga/generator/.Xil/*
fpga/generator/WallyFPGA*
fpga/generator/reports/
fpga/generator/*.log
fpga/generator/*.jou
*.objdump*
*.signature.output
examples/asm/sumtest/sumtest
examples/asm/example/example
examples/C/sum/sum
examples/C/fir/fir
examples/fp/softfloat_demo/softfloat_demo
examples/fp/fpcalc/fpcalc
examples/C/inline/inline
examples/C/sum_mixed/sum_mixed
examples/asm/trap/trap
src/fma/fma16_testgen
linux/devicetree/debug/*
!linux/devicetree/debug/dump-dts.sh
linux/testvector-generation/genCheckpoint.gdb
linux/testvector-generation/silencePipe
linux/testvector-generation/silencePipe.control
linux/testvector-generation/fixBinMem
linux/testvector-generation/qemu-serial
*.dtb
synthDC/WORK
synthDC/alib-52
synthDC/*.log
synthDC/*.svf
synthDC/runs/
synthDC/newRuns
synthDC/ppa/PPAruns
synthDC/ppa/plots
synthDC/wallyplots/
synthDC/runArchive
synthDC/hdl
sim/power.saif
tests/fp/vectors/*.tv
synthDC/Summary.csv
sim/wkdir
tests/custom/work
tests/custom/*/*/*.list
tests/custom/*/*/*.elf
tests/custom/*/*/*.map
tests/custom/*/*/*.memfile
tests/custom/crt0/*.a
tests/custom/*/*.elf*
sim/sd_model.log
fpga/src/sdc/*
fpga/src/sdc.tar.gz
fpga/src/CopiedFiles_do_not_add_to_repo/*
sim/branch.log
/fpga/generator/sim/imp-funcsim.v
/fpga/generator/sim/imp-timesim.sdf
/fpga/generator/sim/imp-timesim.v
/fpga/generator/sim/syn-funcsim.v
external
sim/results
tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/src/*.S
tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/Makefrag
sim/branch_BP_GSHARE10.log
sim/branch_BP_GSHARE16.log
sim/cov/
sim/covhtmlreport/
sim/imperas.log
sim/results-error/
sim/test1.rep
sim/vsim.log
tests/coverage/*.elf
*.elf.memfile
sim/*Cache.log
sim/branch
tests/fp/combined_IF_vectors/IF_vectors/*.tv
/sim/branch-march14.tar.gz
/sim/gshareforward-no-class
/sim/lint-wally_32
/sim/lint-wally_32e
/sim/local16.txt
/sim/localhistory_m6k10_results_april24.txt
/sim/log.log
/sim/obj_dir/Vtestbench.cpp
/sim/obj_dir/Vtestbench.h
/sim/obj_dir/Vtestbench.mk
/sim/obj_dir/Vtestbench__ConstPool_0.cpp
/sim/obj_dir/Vtestbench__Syms.cpp
/sim/obj_dir/Vtestbench__Syms.h
/sim/obj_dir/Vtestbench___024root.h
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0__Slow.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__10.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__11.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1__Slow.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2__Slow.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3__Slow.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4__Slow.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5__Slow.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__6.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__7.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__8.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__9.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0__Slow.cpp
/sim/obj_dir/Vtestbench___024root__Slow.cpp
/sim/obj_dir/Vtestbench___024unit.h
/sim/obj_dir/Vtestbench___024unit__DepSet_hf87c9ffd__0__Slow.cpp
/sim/obj_dir/Vtestbench___024unit__Slow.cpp
/sim/obj_dir/Vtestbench__verFiles.dat
/sim/obj_dir/Vtestbench_classes.mk
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9.h
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0.cpp
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0__Slow.cpp
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0.cpp
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0__Slow.cpp
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__1.cpp
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__Slow.cpp
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20.h
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_h3df7cb71__0.cpp
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0.cpp
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0__Slow.cpp
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__Slow.cpp