FullPathName wallypipelinedsoc/core/PCM[63:0] PCM[63:0] HEXRADIX true STYLE_DIGITAL FullPathName wallypipelinedsoc/core/InstrM[31:0] InstrM[31:0] HEXRADIX true STYLE_DIGITAL FullPathName wallypipelinedsoc/core/InstrValidM InstrValidM true STYLE_DIGITAL FullPathName wallypipelinedsoc/core/TrapM TrapM true STYLE_DIGITAL CPU to LSU label FullPathName wallypipelinedsoc/core/IEUAdrM[63:0] IEUAdrM[63:0] HEXRADIX true STYLE_DIGITAL FullPathName wallypipelinedsoc/core/MemRWM[1:0] MemRWM[1:0] HEXRADIX true STYLE_DIGITAL FullPathName wallypipelinedsoc/core/lsu/WriteDataM[63:0] WriteDataM[63:0] HEXRADIX true STYLE_DIGITAL xIP label FullPathName wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW_5[9:9] MIP_REGW_5[9:9] HEXRADIX true STYLE_DIGITAL PLIC label FullPathName wallypipelinedsoc/uncore/plic.plic/requests[12:1] requests[12:1] HEXRADIX true STYLE_DIGITAL FullPathName wallypipelinedsoc/uncore/plic.plic/intPending[12:1] intPending[12:1] HEXRADIX true STYLE_DIGITAL FullPathName wallypipelinedsoc/uncore/plic.plic/intInProgress[12:1] intInProgress[12:1] HEXRADIX true STYLE_DIGITAL interrupts label wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0] MEDELEG_REGW[63:0] HEXRADIX wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0] MIDELEG_REGW[11:0] HEXRADIX FullPathName wallypipelinedsoc/core/priv.priv/InterruptM InterruptM true STYLE_DIGITAL LSU to Bus label FullPathName wallypipelinedsoc/core/lsu/LSUBusRead LSUBusRead true STYLE_DIGITAL FullPathName wallypipelinedsoc/core/lsu/LSUBusWrite LSUBusWrite true STYLE_DIGITAL FullPathName wallypipelinedsoc/core/lsu/LSUBusAdr[31:0] LSUBusAdr[31:0] HEXRADIX true STYLE_DIGITAL FullPathName wallypipelinedsoc/core/lsu/LSUBusSize[1:0] LSUBusSize[1:0] HEXRADIX true STYLE_DIGITAL FullPathName wallypipelinedsoc/core/lsu/LSUBusHWDATA[63:0] LSUBusHWDATA[63:0] HEXRADIX true STYLE_DIGITAL FullPathName wallypipelinedsoc/core/lsu/LSUBusHRDATA[63:0] LSUBusHRDATA[63:0] HEXRADIX true STYLE_DIGITAL FullPathName wallypipelinedsoc/core/lsu/LSUBusAck LSUBusAck true STYLE_DIGITAL xIE label FullPathName wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_1[1:1] MIE_REGW_1[1:1] HEXRADIX true STYLE_DIGITAL FullPathName wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_2[3:3] MIE_REGW_2[3:3] HEXRADIX true STYLE_DIGITAL FullPathName wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_3[5:5] MIE_REGW_3[5:5] HEXRADIX true STYLE_DIGITAL FullPathName wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_4[7:7] MIE_REGW_4[7:7] HEXRADIX true STYLE_DIGITAL FullPathName wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_5[9:9] MIE_REGW_5[9:9] HEXRADIX true STYLE_DIGITAL FullPathName wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11:11] MIE_REGW[11:11] HEXRADIX true STYLE_DIGITAL sdc label FullPathName wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q r_DAT_ERROR_Q true STYLE_DIGITAL FullPathName wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[4:0] r_curr_state[4:0] HEXRADIX true STYLE_DIGITAL FullPathName wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[3:0] r_curr_state[3:0] HEXRADIX true STYLE_DIGITAL FullPathName wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[3:0] r_curr_state[3:0] HEXRADIX true STYLE_DIGITAL FullPathName wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16 i_ERROR_CRC16 true STYLE_DIGITAL