###########################################
## derivlist.txt
## Wally Derivative Configuration List
##
## Written: David_Harris@hmc.edu, kekim@hmc.edu 
## Created: 29 January 2024
## Modified: 
##
## Purpose: Used by sim/make deriv to generate derivative configurations
##          in config/deriv that are variants of the base configurations.
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
##
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
## may obtain a copy of the License at
##
## https:##solderpad.org/licenses/SHL-2.1/
##
## Unless required by applicable law or agreed to in writing, any work distributed under the 
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
## either express or implied. See the License for the specific language governing permissions 
## and limitations under the License.
################################################################################################

# Format:
# begin a derivative with "deriv <derivative name> <base configuration name> <inherited config name>
# Followed by a list of parameters and their new value in the derivative configuration
# All other parameter values are inherited from the original configuration
# If <inherited config name> is not empty, all the list of parameter changes in the inherited 
# configuration are also applied to this configuration

# buildroot is used for the Linux boot
deriv   buildroot   rv64gc
RESET_VECTOR    64'h1000
UNCORE_RAM_RANGE    64'h0FFFFFFF
UNCORE_RAM_PRELOAD  1
GPIO_LOOPBACK_TEST  0
SPI_LOOPBACK_TEST   0   
UART_PRESCALE       32'd0
PLIC_NUM_SRC        32'd53

# fpga is used for FPGA hardware.  It adds the SDC and DDR (EXT_MEM)
deriv fpga  buildroot 
BOOTROM_PRELOAD     1
UNCORE_RAM_BASE     64'h2000
UNCORE_RAM_RANGE    64'hFFF
EXT_MEM_SUPPORTED   1
EXT_MEM_BASE        64'h80000000
EXT_MEM_RANGE       64'h0FFFFFFF
SDC_SUPPORTED       1
PLIC_SDC_ID         32'd20
BPRED_SIZE          32'd12

# The syn configurations are trimmed down for faster synthesis.  
deriv   syn_rv32e   rv32e
DTIM_RANGE          64'h1FF
IROM_RANGE          64'h1FF
BOOTROM_RANGE       64'h1FF
UNCORE_RAM_RANGE    64'h1FF
WAYSIZEINBYTES      32'd512
NUMWAYS             32'd1
BPRED_SIZE          32'd5
BTB_SIZE            32'd5 

# The other syn configurations have the same trimming
deriv syn_rv32i rv32i syn_rv32e
deriv syn_rv32imc rv32imc syn_rv32e
deriv syn_rv32gc syn_rv32e
deriv syn_rv64i rv64i syn_rv32e
deriv syn_rv64gc rv64gc syn_rv32e

# The syn_sram configurations use SRAM macros
deriv   syn_sram_rv32e   rv32e
DTIM_RANGE          64'h1FF
IROM_RANGE          64'h1FF
USE_SRAM            1

# The other syn configurations have the same trimming
deriv syn_sram_rv32i rv32i syn_sram_rv32e
deriv syn_sram_rv32imc rv32imc syn_sram_rv32e
deriv syn_sram_rv32gc syn_sram_rv32e
deriv syn_sram_rv64i rv64i syn_sram_rv32e
deriv syn_sram_rv64gc rv64gc syn_sram_rv32e

# The following syn configurations gradually turn off features
deriv syn_pmp0_rv64gc syn_rv64gc
PMP_ENTRIES         32'd0
deriv syn_sram_pmp0_rv64gc syn_sram_rv64gc
PMP_ENTRIES         32'd0

deriv syn_noPriv_rv64gc syn_pmp0_rv64gc
ZICSR_SUPPORTED     0
deriv syn_sram_noPriv_rv64gc syn_sram_pmp0_rv64gc
ZICSR_SUPPORTED     0

deriv syn_noFPU_rv64gc syn_noPriv_rv64gc
MISA                (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
deriv syn_sram_noFPU_rv64gc syn_sram_noPriv_rv64gc
MISA                (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)

deriv syn_noMulDiv_rv64gc syn_noFPU_rv64gc
MISA                (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0)
deriv syn_sram_noMulDiv_rv64gc syn_sram_noFPU_rv64gc
MISA                (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0)

deriv syn_noAtomic_rv64gc syn_noMulDiv_rv64gc
MISA                (32'h00000104 | 1 << 18 | 1 << 20)
deriv syn_sram_noAtomic_rv64gc syn_sram_noMulDiv_rv64gc
MISA                (32'h00000104 | 1 << 18 | 1 << 20)

# Divider variants to check logical correctness

deriv div_2_1_rv32gc    rv32gc
RADIX               32'd2
DIVCOPIES           32'd1
IDIV_ON_FPU         0

deriv div_2_2_rv32gc    rv32gc
RADIX               32'd2
DIVCOPIES           32'd2
IDIV_ON_FPU         0

deriv div_2_4_rv32gc    rv32gc
RADIX               32'd2
DIVCOPIES           32'd4
IDIV_ON_FPU         0

deriv div_4_1_rv32gc    rv32gc
RADIX               32'd4
DIVCOPIES           32'd1
IDIV_ON_FPU         0

deriv div_4_2_rv32gc    rv32gc
RADIX               32'd4
IDIV_ON_FPU         0
DIVCOPIES           32'd2
IDIV_ON_FPU         0

deriv div_4_4_rv32gc    rv32gc
RADIX               32'd4
DIVCOPIES           32'd4
IDIV_ON_FPU         0

deriv div_2_1i_rv32gc div_2_1_rv32gc
IDIV_ON_FPU         1

deriv div_2_2i_rv32gc div_2_2_rv32gc
IDIV_ON_FPU         1

deriv div_2_4i_rv32gc div_2_4_rv32gc
IDIV_ON_FPU         1

deriv div_4_1i_rv32gc div_4_1_rv32gc
IDIV_ON_FPU         1

deriv div_4_2i_rv32gc div_4_2_rv32gc
IDIV_ON_FPU         1

deriv div_4_4i_rv32gc div_4_4_rv32gc
IDIV_ON_FPU         1

deriv div_2_1_rv64gc    rv64gc
RADIX               32'd2
DIVCOPIES           32'd1
IDIV_ON_FPU         0

deriv div_2_2_rv64gc    rv64gc
RADIX               32'd2
DIVCOPIES           32'd2
IDIV_ON_FPU         0

deriv div_2_4_rv64gc    rv64gc
RADIX               32'd2
DIVCOPIES           32'd4
IDIV_ON_FPU         0

deriv div_4_1_rv64gc    rv64gc
RADIX               32'd4
DIVCOPIES           32'd1
IDIV_ON_FPU         0

deriv div_4_2_rv64gc    rv64gc
RADIX               32'd4
DIVCOPIES           32'd2
IDIV_ON_FPU         0

deriv div_4_4_rv64gc    rv64gc
RADIX               32'd4
DIVCOPIES           32'd4
IDIV_ON_FPU         0

deriv div_2_1i_rv64gc div_2_1_rv64gc
IDIV_ON_FPU         1

deriv div_2_2i_rv64gc div_2_2_rv64gc
IDIV_ON_FPU         1

deriv div_2_4i_rv64gc div_2_4_rv64gc
IDIV_ON_FPU         1

deriv div_4_1i_rv64gc div_4_1_rv64gc
IDIV_ON_FPU         1

deriv div_4_2i_rv64gc div_4_2_rv64gc
IDIV_ON_FPU         1

deriv div_4_4i_rv64gc div_4_4_rv64gc
IDIV_ON_FPU         1

# RAM latency and Burst mode for bus stress testing

deriv ram_0_0_rv64gc rv64gc
RAM_LATENCY         32'd0
BURST_EN            0

deriv ram_1_0_rv64gc rv64gc
RAM_LATENCY         32'd1
BURST_EN            0

deriv ram_2_0_rv64gc rv64gc
RAM_LATENCY         32'd2
BURST_EN            0

deriv ram_1_1_rv64gc rv64gc
RAM_LATENCY         32'd1
BURST_EN            1

deriv ram_2_1_rv64gc rv64gc
RAM_LATENCY         32'd2
BURST_EN            1

# Branch predictor simulations

deriv bpred_GSHARE_6_16_10_1_rv32gc rv32gc 
BPRED_SIZE          32'd6

deriv bpred_GSHARE_8_16_10_1_rv32gc rv32gc
BPRED_SIZE          32'd8

deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc
BPRED_SIZE          32'd10

deriv bpred_GSHARE_12_16_10_1_rv32gc rv32gc
BPRED_SIZE          32'd12

deriv bpred_GSHARE_14_16_10_1_rv32gc rv32gc
BPRED_SIZE          32'd14

deriv bpred_GSHARE_16_16_10_1_rv32gc rv32gc
BPRED_SIZE          32'd16

deriv bpred_TWOBIT_6_16_10_1_rv32gc bpred_GSHARE_6_16_10_1_rv32gc
BPRED_TYPE          `BP_TWOBIT

deriv bpred_TWOBIT_8_16_10_1_rv32gc bpred_GSHARE_8_16_10_1_rv32gc
BPRED_TYPE          `BP_TWOBIT

deriv bpred_TWOBIT_10_16_10_1_rv32gc bpred_GSHARE_10_16_10_1_rv32gc
BPRED_TYPE          `BP_TWOBIT

deriv bpred_TWOBIT_12_16_10_1_rv32gc bpred_GSHARE_12_16_10_1_rv32gc
BPRED_TYPE          `BP_TWOBIT

deriv bpred_TWOBIT_14_16_10_1_rv32gc bpred_GSHARE_14_16_10_1_rv32gc
BPRED_TYPE          `BP_TWOBIT

deriv bpred_TWOBIT_16_16_10_1_rv32gc bpred_GSHARE_16_16_10_1_rv32gc
BPRED_TYPE          `BP_TWOBIT

deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc
RAS_SIZE         32'd2

deriv bpred_GSHARE_10_3_10_1_rv32gc rv32gc
RAS_SIZE          32'd3

deriv bpred_GSHARE_10_4_10_1_rv32gc rv32gc
RAS_SIZE          32'd4

deriv bpred_GSHARE_10_6_10_1_rv32gc rv32gc
RAS_SIZE          32'd6

deriv bpred_GSHARE_10_10_10_1_rv32gc rv32gc
RAS_SIZE          32'd10

deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc
RAS_SIZE          32'd16

deriv bpred_GSHARE_10_16_6_1_rv32gc rv32gc
BTB_SIZE          32'd6

deriv bpred_GSHARE_10_16_8_1_rv32gc rv32gc
BTB_SIZE          32'd8

deriv bpred_GSHARE_10_16_12_1_rv32gc rv32gc
BTB_SIZE          32'd12

deriv bpred_GSHARE_10_16_14_1_rv32gc rv32gc
BTB_SIZE          32'd14

deriv bpred_GSHARE_10_16_16_1_rv32gc rv32gc
BTB_SIZE          32'd16




deriv bpred_GSHARE_6_16_10_0_rv32gc bpred_GSHARE_6_16_10_1_rv32gc 
INSTR_CLASS_PRED  0

deriv bpred_GSHARE_8_16_10_0_rv32gc bpred_GSHARE_8_16_10_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_GSHARE_10_16_10_0_rv32gc bpred_GSHARE_10_16_10_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_GSHARE_12_16_10_0_rv32gc bpred_GSHARE_12_16_10_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_GSHARE_14_16_10_0_rv32gc bpred_GSHARE_14_16_10_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_GSHARE_16_16_10_0_rv32gc bpred_GSHARE_16_16_10_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_TWOBIT_6_16_10_0_rv32gc bpred_TWOBIT_6_16_10_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_TWOBIT_8_16_10_0_rv32gc bpred_TWOBIT_8_16_10_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_TWOBIT_10_16_10_0_rv32gc bpred_TWOBIT_10_16_10_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_TWOBIT_12_16_10_0_rv32gc bpred_TWOBIT_12_16_10_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_TWOBIT_14_16_10_0_rv32gc bpred_TWOBIT_14_16_10_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_TWOBIT_16_16_10_0_rv32gc bpred_TWOBIT_16_16_10_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_GSHARE_10_2_10_0_rv32gc bpred_GSHARE_10_2_10_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_GSHARE_10_3_10_0_rv32gc bpred_GSHARE_10_3_10_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_GSHARE_10_4_10_0_rv32gc bpred_GSHARE_10_4_10_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_GSHARE_10_6_10_0_rv32gc bpred_GSHARE_10_6_10_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_GSHARE_10_10_10_0_rv32gc bpred_GSHARE_10_10_10_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_GSHARE_10_16_10_0_rv32gc bpred_GSHARE_10_16_10_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_GSHARE_10_16_6_0_rv32gc bpred_GSHARE_10_16_6_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_GSHARE_10_16_8_0_rv32gc bpred_GSHARE_10_16_8_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_GSHARE_10_16_12_0_rv32gc bpred_GSHARE_10_16_12_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_GSHARE_10_16_14_0_rv32gc bpred_GSHARE_10_16_14_1_rv32gc
INSTR_CLASS_PRED          0

deriv bpred_GSHARE_10_16_16_0_rv32gc bpred_GSHARE_10_16_16_1_rv32gc
INSTR_CLASS_PRED          0

# Cache configurations

deriv noicache_rv32gc rv32gc
ICACHE_SUPPORTED    0
VIRTMEM_SUPPORTED    0

deriv nodcache_rv32gc rv32gc
DCACHE_SUPPORTED    0

deriv nocache_rv32gc rv32gc
ICACHE_SUPPORTED    0
DCACHE_SUPPORTED    0

deriv noicache_rv64gc rv64gc
ICACHE_SUPPORTED    0
VIRTMEM_SUPPORTED    0
SVPBMT_SUPPORTED    0
SVNAPOT_SUPPORTED   0

deriv nodcache_rv64gc rv64gc
DCACHE_SUPPORTED    0
VIRTMEM_SUPPORTED    0
ZICBOM_SUPPORTED    0
ZICBOZ_SUPPORTED    0
SVPBMT_SUPPORTED    0
SVNAPOT_SUPPORTED   0
MISA                (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12)

deriv nocache_rv64gc rv64gc
ICACHE_SUPPORTED    0
DCACHE_SUPPORTED    0
VIRTMEM_SUPPORTED    0
ZICBOM_SUPPORTED    0
ZICBOZ_SUPPORTED    0
SVPBMT_SUPPORTED    0
SVNAPOT_SUPPORTED   0
MISA                (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12)

deriv way_1_4096_512_rv32gc rv32gc
DCACHE_NUMWAYS      32'd1
DCACHE_WAYSIZEINBYTES 32'd4096
DCACHE_LINELENINBITS 32'd512
ICACHE_NUMWAYS      32'd1
ICACHE_WAYSIZEINBYTES 32'd4096
ICACHE_LINELENINBITS 32'd512

deriv way_2_4096_512_rv32gc way_1_4096_512_rv32gc
DCACHE_NUMWAYS      32'd1
ICACHE_NUMWAYS      32'd1

deriv way_4_4096_512_rv32gc way_1_4096_512_rv32gc
DCACHE_NUMWAYS      32'd4
ICACHE_NUMWAYS      32'd4

deriv way_8_4096_512_rv32gc way_1_4096_512_rv32gc
DCACHE_NUMWAYS      32'd8
ICACHE_NUMWAYS      32'd8

deriv way_4_2048_512_rv32gc way_4_4096_512_rv32gc
DCACHE_WAYSIZEINBYTES 32'd2048
ICACHE_WAYSIZEINBYTES 32'd2048

deriv way_4_4096_256_rv32gc way_4_4096_512_rv32gc
DCACHE_LINELENINBITS 32'd256
ICACHE_LINELENINBITS 32'd256

deriv way_1_4096_512_rv64gc rv64gc
DCACHE_NUMWAYS      32'd1
DCACHE_WAYSIZEINBYTES 32'd4096
DCACHE_LINELENINBITS 32'd512
ICACHE_NUMWAYS      32'd1
ICACHE_WAYSIZEINBYTES 32'd4096
ICACHE_LINELENINBITS 32'd512

deriv way_2_4096_512_rv64gc way_1_4096_512_rv64gc
DCACHE_NUMWAYS      32'd1
ICACHE_NUMWAYS      32'd1

deriv way_4_4096_512_rv64gc way_1_4096_512_rv64gc
DCACHE_NUMWAYS      32'd4
ICACHE_NUMWAYS      32'd4

deriv way_8_4096_512_rv64gc way_1_4096_512_rv64gc
DCACHE_NUMWAYS      32'd8
ICACHE_NUMWAYS      32'd8

deriv way_4_2048_512_rv64gc way_4_4096_512_rv64gc
DCACHE_WAYSIZEINBYTES 32'd2048
ICACHE_WAYSIZEINBYTES 32'd2048

deriv way_4_4096_256_rv64gc way_4_4096_512_rv64gc
DCACHE_LINELENINBITS 32'd256
ICACHE_LINELENINBITS 32'd256

deriv way_4_4096_1024_rv64gc way_4_4096_512_rv64gc
DCACHE_LINELENINBITS 32'd1024
ICACHE_LINELENINBITS 32'd1024

# TLB Size variants

deriv tlb2_rv32gc rv32gc
ITLB_ENTRIES 32'd2
DTLB_ENTRIES 32'd2

deriv tlb16_rv32gc rv32gc
ITLB_ENTRIES 32'd16
DTLB_ENTRIES 32'd16

deriv tlb2_rv64gc rv64gc
ITLB_ENTRIES 32'd2
DTLB_ENTRIES 32'd2

deriv tlb16_rv64gc rv64gc
ITLB_ENTRIES 32'd16
DTLB_ENTRIES 32'd16

# Feature variants

deriv misaligned_rv32gc rv32gc
ZICCLSM_SUPPORTED 1

deriv nomisaligned_rv64gc rv64gc
ZICCLSM_SUPPORTED 0

deriv nobigendian_rv32gc rv32gc
BIGENDIAN_SUPPORTED 0

deriv nobigendian_rv64gc rv64gc
BIGENDIAN_SUPPORTED 0

# Floating-point modes supported

deriv f_rv32gc rv32gc
MISA    (32'h00000104 |  1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fh_rv32gc rv32gc
MISA    (32'h00000104 |  1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fd_rv32gc rv32gc
MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fdh_rv32gc rv32gc
MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdq_rv32gc rv32gc
MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fdqh_rv32gc rv32gc
MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv f_rv64gc rv64gc
MISA    (32'h00000104 |  1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fh_rv64gc rv64gc
MISA    (32'h00000104 |  1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fd_rv64gc rv64gc
MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fdh_rv64gc rv64gc
MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdq_rv64gc rv64gc
MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fdqh_rv64gc rv64gc
MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

# IEEE compatible variants for TestFloat

deriv f_ieee_rv32gc f_rv32gc
IEEE754     1

deriv fh_ieee_rv32gc fh_rv32gc
IEEE754     1

deriv fd_ieee_rv32gc fd_rv32gc
IEEE754     1

deriv fdh_ieee_rv32gc fdh_rv32gc
IEEE754     1

deriv fdq_ieee_rv32gc fdq_rv32gc
IEEE754     1

deriv fdqh_ieee_rv32gc fdqh_rv32gc
IEEE754     1

deriv f_ieee_rv64gc f_rv64gc
IEEE754     1

deriv fh_ieee_rv64gc fh_rv64gc
IEEE754     1

deriv fd_ieee_rv64gc fd_rv64gc
IEEE754     1

deriv fdh_ieee_rv64gc fdh_rv64gc
IEEE754     1

deriv fdq_ieee_rv64gc fdq_rv64gc
IEEE754     1

deriv fdqh_ieee_rv64gc fdqh_rv64gc
IEEE754     1

#### MORE DIVIDER variants

#### F_only, RK variable
deriv f_div_2_1_rv32gc    div_2_1_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv f_div_2_2_rv32gc    div_2_2_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv f_div_2_4_rv32gc    div_2_4_rv32gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv f_div_4_1_rv32gc    div_4_1_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv f_div_4_2_rv32gc    div_4_2_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv f_div_4_4_rv32gc    div_4_4_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv f_div_2_1_rv64gc    div_2_1_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv f_div_2_2_rv64gc    div_2_2_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv f_div_2_4_rv64gc    div_2_4_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv f_div_4_1_rv64gc    div_4_1_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv f_div_4_2_rv64gc    div_4_2_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv f_div_4_4_rv64gc    div_4_4_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0


#### FH_only, RK variable
deriv fh_div_2_1_rv32gc    div_2_1_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fh_div_2_2_rv32gc    div_2_2_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fh_div_2_4_rv32gc    div_2_4_rv32gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fh_div_4_1_rv32gc    div_4_1_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fh_div_4_2_rv32gc    div_4_2_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fh_div_4_4_rv32gc    div_4_4_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fh_div_2_1_rv64gc    div_2_1_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fh_div_2_2_rv64gc    div_2_2_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fh_div_2_4_rv64gc    div_2_4_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fh_div_4_1_rv64gc    div_4_1_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fh_div_4_2_rv64gc    div_4_2_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fh_div_4_4_rv64gc    div_4_4_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

# FD only , rk variable

deriv fd_div_2_1_rv32gc    div_2_1_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fd_div_2_2_rv32gc    div_2_2_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fd_div_2_4_rv32gc    div_2_4_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fd_div_4_1_rv32gc    div_4_1_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fd_div_4_2_rv32gc    div_4_2_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fd_div_4_4_rv32gc    div_4_4_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fd_div_2_1_rv64gc    div_2_1_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fd_div_2_2_rv64gc    div_2_2_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fd_div_2_4_rv64gc    div_2_4_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fd_div_4_1_rv64gc    div_4_1_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fd_div_4_2_rv64gc    div_4_2_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fd_div_4_4_rv64gc    div_4_4_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0


# FDH only , rk variable

deriv fdh_div_2_1_rv32gc    div_2_1_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdh_div_2_2_rv32gc    div_2_2_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdh_div_2_4_rv32gc    div_2_4_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdh_div_4_1_rv32gc    div_4_1_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdh_div_4_2_rv32gc    div_4_2_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdh_div_4_4_rv32gc    div_4_4_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdh_div_2_1_rv64gc    div_2_1_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdh_div_2_2_rv64gc    div_2_2_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdh_div_2_4_rv64gc    div_2_4_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdh_div_4_1_rv64gc    div_4_1_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdh_div_4_2_rv64gc    div_4_2_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdh_div_4_4_rv64gc    div_4_4_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

# FDQ only , rk variable

deriv fdq_div_2_1_rv32gc    div_2_1_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fdq_div_2_2_rv32gc    div_2_2_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fdq_div_2_4_rv32gc    div_2_4_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fdq_div_4_1_rv32gc    div_4_1_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fdq_div_4_2_rv32gc    div_4_2_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fdq_div_4_4_rv32gc    div_4_4_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fdq_div_2_1_rv64gc    div_2_1_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fdq_div_2_2_rv64gc    div_2_2_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fdq_div_2_4_rv64gc    div_2_4_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fdq_div_4_1_rv64gc    div_4_1_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fdq_div_4_2_rv64gc    div_4_2_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

deriv fdq_div_4_4_rv64gc    div_4_4_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   0

# FDQH only , rk variable

deriv fdqh_div_2_1_rv32gc    div_2_1_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdqh_div_2_2_rv32gc    div_2_2_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdqh_div_2_4_rv32gc    div_2_4_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdqh_div_4_1_rv32gc    div_4_1_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdqh_div_4_2_rv32gc    div_4_2_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdqh_div_4_4_rv32gc    div_4_4_rv32gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdqh_div_2_1_rv64gc    div_2_1_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdqh_div_2_2_rv64gc    div_2_2_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdqh_div_2_4_rv64gc    div_2_4_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdqh_div_4_1_rv64gc    div_4_1_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdqh_div_4_2_rv64gc    div_4_2_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

deriv fdqh_div_4_4_rv64gc    div_4_4_rv64gc    
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED   1

#### DIVIDER VARIANTS WITH IEEE

deriv f_ieee_div_2_1_rv32gc    f_div_2_1_rv32gc    
IEEE754         1

deriv f_ieee_div_2_2_rv32gc    f_div_2_2_rv32gc    
IEEE754         1

deriv f_ieee_div_2_4_rv32gc    f_div_2_4_rv32gc    
IEEE754         1

deriv f_ieee_div_4_1_rv32gc    f_div_4_1_rv32gc    
IEEE754         1

deriv f_ieee_div_4_2_rv32gc    f_div_4_2_rv32gc    
IEEE754         1

deriv f_ieee_div_4_4_rv32gc    f_div_4_4_rv32gc    
IEEE754         1

deriv f_ieee_div_2_1_rv64gc    f_div_2_1_rv64gc    
IEEE754         1

deriv f_ieee_div_2_2_rv64gc    f_div_2_2_rv64gc    
IEEE754         1

deriv f_ieee_div_2_4_rv64gc    f_div_2_4_rv64gc    
IEEE754         1

deriv f_ieee_div_4_1_rv64gc    f_div_4_1_rv64gc    
IEEE754         1

deriv f_ieee_div_4_2_rv64gc    f_div_4_2_rv64gc    
IEEE754         1

deriv f_ieee_div_4_4_rv64gc    f_div_4_4_rv64gc    
IEEE754         1

#### FH_only, RK variable
deriv fh_ieee_div_2_1_rv32gc    fh_div_2_1_rv32gc    
IEEE754         1

deriv fh_ieee_div_2_2_rv32gc    fh_div_2_2_rv32gc    
IEEE754         1

deriv fh_ieee_div_2_4_rv32gc    fh_div_2_4_rv32gc    
IEEE754         1

deriv fh_ieee_div_4_1_rv32gc    fh_div_4_1_rv32gc    
IEEE754         1

deriv fh_ieee_div_4_2_rv32gc    fh_div_4_2_rv32gc    
IEEE754         1

deriv fh_ieee_div_4_4_rv32gc    fh_div_4_4_rv32gc    
IEEE754         1

deriv fh_ieee_div_2_1_rv64gc    fh_div_2_1_rv64gc    
IEEE754         1

deriv fh_ieee_div_2_2_rv64gc    fh_div_2_2_rv64gc    
IEEE754         1

deriv fh_ieee_div_2_4_rv64gc    fh_div_2_4_rv64gc    
IEEE754         1

deriv fh_ieee_div_4_1_rv64gc    fh_div_4_1_rv64gc    
IEEE754         1

deriv fh_ieee_div_4_2_rv64gc    fh_div_4_2_rv64gc    
IEEE754         1

deriv fh_ieee_div_4_4_rv64gc    fh_div_4_4_rv64gc    
IEEE754         1
# FD only , rk variable

deriv fd_ieee_div_2_1_rv32gc    fd_div_2_1_rv32gc    
IEEE754         1

deriv fd_ieee_div_2_2_rv32gc    fd_div_2_2_rv32gc    
IEEE754         1

deriv fd_ieee_div_2_4_rv32gc    fd_div_2_4_rv32gc    
IEEE754         1

deriv fd_ieee_div_4_1_rv32gc    fd_div_4_1_rv32gc    
IEEE754         1

deriv fd_ieee_div_4_2_rv32gc    fd_div_4_2_rv32gc    
IEEE754         1

deriv fd_ieee_div_4_4_rv32gc    fd_div_4_4_rv32gc    
IEEE754         1

deriv fd_ieee_div_2_1_rv64gc    fd_div_2_1_rv64gc    
IEEE754         1

deriv fd_ieee_div_2_2_rv64gc    fd_div_2_2_rv64gc    
IEEE754         1

deriv fd_ieee_div_2_4_rv64gc    fd_div_2_4_rv64gc    
IEEE754         1

deriv fd_ieee_div_4_1_rv64gc    fd_div_4_1_rv64gc    
IEEE754         1

deriv fd_ieee_div_4_2_rv64gc    fd_div_4_2_rv64gc    
IEEE754         1

deriv fd_ieee_div_4_4_rv64gc    fd_div_4_4_rv64gc    
IEEE754         1

# FDH only , rk variable

deriv fdh_ieee_div_2_1_rv32gc    fdh_div_2_1_rv32gc    
IEEE754         1

deriv fdh_ieee_div_2_2_rv32gc    fdh_div_2_2_rv32gc    
IEEE754         1

deriv fdh_ieee_div_2_4_rv32gc    fdh_div_2_4_rv32gc    
IEEE754         1

deriv fdh_ieee_div_4_1_rv32gc    fdh_div_4_1_rv32gc    
IEEE754         1

deriv fdh_ieee_div_4_2_rv32gc    fdh_div_4_2_rv32gc    
IEEE754         1

deriv fdh_ieee_div_4_4_rv32gc    fdh_div_4_4_rv32gc    
IEEE754         1

deriv fdh_ieee_div_2_1_rv64gc    fdh_div_2_1_rv64gc    
IEEE754         1

deriv fdh_ieee_div_2_2_rv64gc    fdh_div_2_2_rv64gc    
IEEE754         1

deriv fdh_ieee_div_2_4_rv64gc    fdh_div_2_4_rv64gc    
IEEE754         1

deriv fdh_ieee_div_4_1_rv64gc    fdh_div_4_1_rv64gc    
IEEE754         1

deriv fdh_ieee_div_4_2_rv64gc    fdh_div_4_2_rv64gc    
IEEE754         1

deriv fdh_ieee_div_4_4_rv64gc    fdh_div_4_4_rv64gc    
IEEE754         1
# FDQ only , rk variable

deriv fdq_ieee_div_2_1_rv32gc    fdq_div_2_1_rv32gc    
IEEE754         1

deriv fdq_ieee_div_2_2_rv32gc    fdq_div_2_2_rv32gc    
IEEE754         1

deriv fdq_ieee_div_2_4_rv32gc    fdq_div_2_4_rv32gc    
IEEE754         1

deriv fdq_ieee_div_4_1_rv32gc    fdq_div_4_1_rv32gc    
IEEE754         1

deriv fdq_ieee_div_4_2_rv32gc    fdq_div_4_2_rv32gc    
IEEE754         1

deriv fdq_ieee_div_4_4_rv32gc    fdq_div_4_4_rv32gc    
IEEE754         1

deriv fdq_ieee_div_2_1_rv64gc    fdq_div_2_1_rv64gc    
IEEE754         1

deriv fdq_ieee_div_2_2_rv64gc    fdq_div_2_2_rv64gc    
IEEE754         1

deriv fdq_ieee_div_2_4_rv64gc    fdq_div_2_4_rv64gc    
IEEE754         1

deriv fdq_ieee_div_4_1_rv64gc    fdq_div_4_1_rv64gc    
IEEE754         1

deriv fdq_ieee_div_4_2_rv64gc    fdq_div_4_2_rv64gc    
IEEE754         1

deriv fdq_ieee_div_4_4_rv64gc    fdq_div_4_4_rv64gc    
IEEE754         1

# FDQH only , rk variable

deriv fdqh_ieee_div_2_1_rv32gc    fdqh_div_2_1_rv32gc    
IEEE754         1

deriv fdqh_ieee_div_2_2_rv32gc    fdqh_div_2_2_rv32gc    
IEEE754         1

deriv fdqh_ieee_div_2_4_rv32gc    fdqh_div_2_4_rv32gc    
IEEE754         1

deriv fdqh_ieee_div_4_1_rv32gc    fdqh_div_4_1_rv32gc    
IEEE754         1

deriv fdqh_ieee_div_4_2_rv32gc    fdqh_div_4_2_rv32gc    
IEEE754         1

deriv fdqh_ieee_div_4_4_rv32gc    fdqh_div_4_4_rv32gc    
IEEE754         1

deriv fdqh_ieee_div_2_1_rv64gc    fdqh_div_2_1_rv64gc    
IEEE754         1

deriv fdqh_ieee_div_2_2_rv64gc    fdqh_div_2_2_rv64gc    
IEEE754         1

deriv fdqh_ieee_div_2_4_rv64gc    fdqh_div_2_4_rv64gc    
IEEE754         1

deriv fdqh_ieee_div_4_1_rv64gc    fdqh_div_4_1_rv64gc    
IEEE754         1

deriv fdqh_ieee_div_4_2_rv64gc    fdqh_div_4_2_rv64gc    
IEEE754         1

deriv fdqh_ieee_div_4_4_rv64gc    fdqh_div_4_4_rv64gc    
IEEE754         1

#### DIVIDER VARIANTS WITH IDIV ON FPU

deriv f_ieee_div_2_1i_rv32gc f_ieee_div_2_1_rv32gc        
IDIV_ON_FPU     1

deriv f_ieee_div_2_2i_rv32gc f_ieee_div_2_2_rv32gc        
IDIV_ON_FPU     1

deriv f_ieee_div_2_4i_rv32gc f_ieee_div_2_4_rv32gc        
IDIV_ON_FPU     1

deriv f_ieee_div_4_1i_rv32gc f_ieee_div_4_1_rv32gc        
IDIV_ON_FPU     1

deriv f_ieee_div_4_2i_rv32gc f_ieee_div_4_2_rv32gc        
IDIV_ON_FPU     1

deriv f_ieee_div_4_4i_rv32gc f_ieee_div_4_4_rv32gc        
IDIV_ON_FPU     1

deriv f_ieee_div_2_1i_rv64gc f_ieee_div_2_1_rv64gc        
IDIV_ON_FPU     1

deriv f_ieee_div_2_2i_rv64gc f_ieee_div_2_2_rv64gc        
IDIV_ON_FPU     1

deriv f_ieee_div_2_4i_rv64gc f_ieee_div_2_4_rv64gc        
IDIV_ON_FPU     1

deriv f_ieee_div_4_1i_rv64gc f_ieee_div_4_1_rv64gc        
IDIV_ON_FPU     1

deriv f_ieee_div_4_2i_rv64gc f_ieee_div_4_2_rv64gc        
IDIV_ON_FPU     1

deriv f_ieee_div_4_4i_rv64gc f_ieee_div_4_4_rv64gc        
IDIV_ON_FPU     1

#### FH_only, RK variable
deriv fh_ieee_div_2_1i_rv32gc fh_ieee_div_2_1_rv32gc        
IDIV_ON_FPU     1

deriv fh_ieee_div_2_2i_rv32gc fh_ieee_div_2_2_rv32gc        
IDIV_ON_FPU     1

deriv fh_ieee_div_2_4i_rv32gc fh_ieee_div_2_4_rv32gc        
IDIV_ON_FPU     1

deriv fh_ieee_div_4_1i_rv32gc fh_ieee_div_4_1_rv32gc        
IDIV_ON_FPU     1

deriv fh_ieee_div_4_2i_rv32gc fh_ieee_div_4_2_rv32gc        
IDIV_ON_FPU     1

deriv fh_ieee_div_4_4i_rv32gc fh_ieee_div_4_4_rv32gc        
IDIV_ON_FPU     1

deriv fh_ieee_div_2_1i_rv64gc fh_ieee_div_2_1_rv64gc        
IDIV_ON_FPU     1

deriv fh_ieee_div_2_2i_rv64gc fh_ieee_div_2_2_rv64gc        
IDIV_ON_FPU     1

deriv fh_ieee_div_2_4i_rv64gc fh_ieee_div_2_4_rv64gc        
IDIV_ON_FPU     1

deriv fh_ieee_div_4_1i_rv64gc fh_ieee_div_4_1_rv64gc        
IDIV_ON_FPU     1

deriv fh_ieee_div_4_2i_rv64gc fh_ieee_div_4_2_rv64gc        
IDIV_ON_FPU     1

deriv fh_ieee_div_4_4i_rv64gc fh_ieee_div_4_4_rv64gc        
IDIV_ON_FPU     1

# FD only , rk variable

deriv fd_ieee_div_2_1i_rv32gc fd_ieee_div_2_1_rv32gc        
IDIV_ON_FPU     1

deriv fd_ieee_div_2_2i_rv32gc fd_ieee_div_2_2_rv32gc        
IDIV_ON_FPU     1

deriv fd_ieee_div_2_4i_rv32gc fd_ieee_div_2_4_rv32gc        
IDIV_ON_FPU     1

deriv fd_ieee_div_4_1i_rv32gc fd_ieee_div_4_1_rv32gc        
IDIV_ON_FPU     1

deriv fd_ieee_div_4_2i_rv32gc fd_ieee_div_4_2_rv32gc        
IDIV_ON_FPU     1

deriv fd_ieee_div_4_4i_rv32gc fd_ieee_div_4_4_rv32gc        
IDIV_ON_FPU     1

deriv fd_ieee_div_2_1i_rv64gc fd_ieee_div_2_1_rv64gc        
IDIV_ON_FPU     1

deriv fd_ieee_div_2_2i_rv64gc fd_ieee_div_2_2_rv64gc        
IDIV_ON_FPU     1

deriv fd_ieee_div_2_4i_rv64gc fd_ieee_div_2_4_rv64gc        
IDIV_ON_FPU     1

deriv fd_ieee_div_4_1i_rv64gc fd_ieee_div_4_1_rv64gc        
IDIV_ON_FPU     1

deriv fd_ieee_div_4_2i_rv64gc fd_ieee_div_4_2_rv64gc        
IDIV_ON_FPU     1

deriv fd_ieee_div_4_4i_rv64gc fd_ieee_div_4_4_rv64gc        
IDIV_ON_FPU     1

# FDH only , rk variable

deriv fdh_ieee_div_2_1i_rv32gc fdh_ieee_div_2_1_rv32gc        
IDIV_ON_FPU     1

deriv fdh_ieee_div_2_2i_rv32gc fdh_ieee_div_2_2_rv32gc        
IDIV_ON_FPU     1

deriv fdh_ieee_div_2_4i_rv32gc fdh_ieee_div_2_4_rv32gc        
IDIV_ON_FPU     1

deriv fdh_ieee_div_4_1i_rv32gc fdh_ieee_div_4_1_rv32gc        
IDIV_ON_FPU     1

deriv fdh_ieee_div_4_2i_rv32gc fdh_ieee_div_4_2_rv32gc        
IDIV_ON_FPU     1

deriv fdh_ieee_div_4_4i_rv32gc fdh_ieee_div_4_4_rv32gc        
IDIV_ON_FPU     1

deriv fdh_ieee_div_2_1i_rv64gc fdh_ieee_div_2_1_rv64gc        
IDIV_ON_FPU     1

deriv fdh_ieee_div_2_2i_rv64gc fdh_ieee_div_2_2_rv64gc        
IDIV_ON_FPU     1

deriv fdh_ieee_div_2_4i_rv64gc fdh_ieee_div_2_4_rv64gc        
IDIV_ON_FPU     1

deriv fdh_ieee_div_4_1i_rv64gc fdh_ieee_div_4_1_rv64gc        
IDIV_ON_FPU     1

deriv fdh_ieee_div_4_2i_rv64gc fdh_ieee_div_4_2_rv64gc        
IDIV_ON_FPU     1

deriv fdh_ieee_div_4_4i_rv64gc fdh_ieee_div_4_4_rv64gc        
IDIV_ON_FPU     1

# FDQ only , rk variable

deriv fdq_ieee_div_2_1i_rv32gc fdq_ieee_div_2_1_rv32gc        
IDIV_ON_FPU     1

deriv fdq_ieee_div_2_2i_rv32gc fdq_ieee_div_2_2_rv32gc        
IDIV_ON_FPU     1

deriv fdq_ieee_div_2_4i_rv32gc fdq_ieee_div_2_4_rv32gc        
IDIV_ON_FPU     1

deriv fdq_ieee_div_4_1i_rv32gc fdq_ieee_div_4_1_rv32gc        
IDIV_ON_FPU     1

deriv fdq_ieee_div_4_2i_rv32gc fdq_ieee_div_4_2_rv32gc        
IDIV_ON_FPU     1

deriv fdq_ieee_div_4_4i_rv32gc fdq_ieee_div_4_4_rv32gc        
IDIV_ON_FPU     1

deriv fdq_ieee_div_2_1i_rv64gc fdq_ieee_div_2_1_rv64gc        
IDIV_ON_FPU     1

deriv fdq_ieee_div_2_2i_rv64gc fdq_ieee_div_2_2_rv64gc        
IDIV_ON_FPU     1

deriv fdq_ieee_div_2_4i_rv64gc fdq_ieee_div_2_4_rv64gc        
IDIV_ON_FPU     1

deriv fdq_ieee_div_4_1i_rv64gc fdq_ieee_div_4_1_rv64gc        
IDIV_ON_FPU     1

deriv fdq_ieee_div_4_2i_rv64gc fdq_ieee_div_4_2_rv64gc        
IDIV_ON_FPU     1

deriv fdq_ieee_div_4_4i_rv64gc fdq_ieee_div_4_4_rv64gc        
IDIV_ON_FPU     1

# FDQH only , rk variable

deriv fdqh_ieee_div_2_1i_rv32gc fdqh_ieee_div_2_1_rv32gc        
IDIV_ON_FPU     1

deriv fdqh_ieee_div_2_2i_rv32gc fdqh_ieee_div_2_2_rv32gc        
IDIV_ON_FPU     1

deriv fdqh_ieee_div_2_4i_rv32gc fdqh_ieee_div_2_4_rv32gc        
IDIV_ON_FPU     1

deriv fdqh_ieee_div_4_1i_rv32gc fdqh_ieee_div_4_1_rv32gc        
IDIV_ON_FPU     1

deriv fdqh_ieee_div_4_2i_rv32gc fdqh_ieee_div_4_2_rv32gc        
IDIV_ON_FPU     1

deriv fdqh_ieee_div_4_4i_rv32gc fdqh_ieee_div_4_4_rv32gc        
IDIV_ON_FPU     1

deriv fdqh_ieee_div_2_1i_rv64gc fdqh_ieee_div_2_1_rv64gc        
IDIV_ON_FPU     1

deriv fdqh_ieee_div_2_2i_rv64gc fdqh_ieee_div_2_2_rv64gc        
IDIV_ON_FPU     1

deriv fdqh_ieee_div_2_4i_rv64gc fdqh_ieee_div_2_4_rv64gc        
IDIV_ON_FPU     1

deriv fdqh_ieee_div_4_1i_rv64gc fdqh_ieee_div_4_1_rv64gc        
IDIV_ON_FPU     1

deriv fdqh_ieee_div_4_2i_rv64gc fdqh_ieee_div_4_2_rv64gc        
IDIV_ON_FPU     1

deriv fdqh_ieee_div_4_4i_rv64gc fdqh_ieee_div_4_4_rv64gc        
IDIV_ON_FPU     1