wally/wallypipelinedcore.sv: logic             PCM
wally/wallypipelinedcore.sv: logic    TrapM
wally/wallypipelinedcore.sv: logic                InstrValidM
wally/wallypipelinedcore.sv: logic                 InstrM
lsu/lsu.sv: logic        IEUAdrM
lsu/lsu.sv: logic       MemRWM
mmu/hptw.sv: logic	   SATP_REGW
uncore/spi_apb.sv: logic ShiftIn
uncore/spi_apb.sv: logic  ReceiveShiftReg
uncore/spi_apb.sv: logic  SCLKenable
uncore/spi_apb.sv: logic  SampleEdge
uncore/spi_apb.sv: logic  Active
uncore/spi_apb.sv: statetype state
uncore/spi_apb.sv: typedef rsrstatetype
uncore/spi_apb.sv: logic SPICLK
uncore/spi_apb.sv: logic SPIOut
uncore/spi_apb.sv: logic SPICS
uncore/spi_apb.sv: logic SckMode
uncore/spi_apb.sv: logic SckDiv
uncore/spi_apb.sv: logic ShiftEdge
uncore/spi_apb.sv: logic TransmitShiftRegLoadSingleCycle
uncore/spi_apb.sv: logic TransmitShiftReg
uncore/spi_apb.sv: logic TransmitData
uncore/spi_apb.sv: logic ReceiveData
uncore/spi_apb.sv: logic ReceiveShiftRegEndian
uncore/spi_apb.sv: logic TransmitShiftReg
uncore/spi_apb.sv: logic TransmitShift
uncore/spi_apb.sv: logic ReceiveShiftFullDelay
uncore/spi_apb.sv: logic TransmitShiftEmpty
uncore/spi_apb.sv: logic ReceiveFIFOWriteFull
uncore/spi_apb.sv: logic ReceiveFIFOReadIncrement
uncore/spi_apb.sv: logic ReceiveFIFOReadEmpty
uncore/spi_apb.sv: logic TransmitFIFOWriteIncrement
uncore/spi_apb.sv: logic TransmitFIFOReadIncrement
uncore/spi_apb.sv: logic TransmitFIFOWriteFull
uncore/spi_apb.sv: logic TransmitFIFOReadEmpty