# General file extensions to ignore
.nfs*
*.objdump*
*.o
*.d
*.a
*.vstf
*.vcd
*.signature.output
*.dtb
*.log
*.map
*.elf*
*.list

# General directories to ignore
.vscode/
__pycache__/
**/work*
/**/obj_dir*
/**/gmon*

#External repos
addins/riscv-arch-test/Makefile.include
addins/riscv-tests/target
addins/TestFloat-3e/build/Linux-x86_64-GCC/*

# Tests
tests/riscof/config32.ini
tests/riscof/config32e.ini
tests/riscof/config64.ini
tests/riscof/riscof_work/
tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/**
tests/fp/vectors/*.tv
tests/fp/combined_IF_vectors/IF_vectors/*.tv
tests/custom/*/*/
tests/custom/*/*/*.memfile
tests/riscvdv
tests/functcov

# Linux
linux/buildroot
linux/testvector-generation/boottrace.S
linux/devicetree/debug/*
!linux/devicetree/debug/dump-dts.sh
linux/testvector-generation/genCheckpoint.gdb
linux/testvector-generation/silencePipe
linux/testvector-generation/silencePipe.control
linux/testvector-generation/fixBinMem
linux/testvector-generation/qemu-serial

# FPGA
fpga/generator/IP
fpga/generator/vivado.*
fpga/generator/.Xil/*
fpga/generator/WallyFPGA*
fpga/generator/reports/
fpga/generator/*.jou
fpga/src/sdc/*
fpga/src/sdc.tar.gz
fpga/src/CopiedFiles_do_not_add_to_repo/*
fpga/generator/sim/imp-funcsim.v
fpga/generator/sim/imp-timesim.sdf
fpga/generator/sim/imp-timesim.v
fpga/generator/sim/syn-funcsim.v
fpga/rvvidaemon/rvvidaemon
fpga/zsbl/OBJ/*
fpga/zsbl/bin/*
fpga/src/boot.mem
fpga/src/data.mem

# Synthesis
synthDC/WORK
synthDC/alib-52
synthDC/*.svf
synthDC/runs/
synthDC/newRuns
synthDC/ppa/PPAruns
synthDC/ppa/plots
synthDC/wallyplots/
synthDC/runArchive
synthDC/hdl
synthDC/Summary.csv

# Benchmarks
benchmarks/embench/wally*.json
benchmarks/embench/run*
benchmarks/coremark/coremark_results.csv

# Simulation
sim/*.svg
sim/power.saif
sim/results
sim/results-error/
sim/test1.rep
sim/branch
sim/branch-march14.tar.gz
sim/gshareforward-no-class
sim/local16.txt
sim/localhistory_m6k10_results_april24.txt
sim/cfi/*
sim/branch/*
sim/covhtmlreport/

# Questa
sim/questa/logs
sim/questa/wkdir
sim/questa/ucdb
sim/questa/cov
sim/questa/fcov
sim/questa/fcovrvvi
sim/questa/fcovrvvi_logs
sim/questa/fcovrvvi_ucdb
sim/questa/fcov_logs
sim/questa/fcov_ucdb
sim/questa/functcov_logs
sim/questa/functcov_ucdbs
sim/questa/functcov
sim/questa/riscv.ucdb
transcript
vsim.wlf
wlft*

# VCS
sim/vcs/logs
sim/vcs/wkdir
sim/vcs/ucdb
sim/vcs/csrc
sim/vcs/profileReport*
sim/vcs/program.out
sim/vcs/sim_out*
sim/vcs/simprofile_dir
sim/vcs/ucli.key
sim/vcs/verdi_config_file
sim/vcs/vcdplus.vpd
sim/vcs/simprofile*

# Verilator
sim/verilator/logs
sim/verilator/wkdir

# Examples
examples/verilog/fulladder/csrc/
examples/verilog/fulladder/profileReport.html
examples/verilog/fulladder/profileReport.json
examples/verilog/fulladder/profileReport.txt
examples/verilog/fulladder/profileReport/
examples/verilog/fulladder/simprofile_dir/
examples/verilog/fulladder/simv.daidir/
examples/verilog/fulladder/ucli.key
examples/verilog/fulladder/verdi_config_file
examples/fp/softfloat_demo/softfloat_demo
examples/fp/softfloat_demo/softfloat_demoDP
examples/fp/softfloat_demo/softfloat_demoQP
examples/fp/softfloat_demo/softfloat_demoSP
examples/fp/fpcalc/fpcalc
examples/fp/sqrttest/sqrttest
examples/crypto/gfmul/gfmul
examples/C/fir/fir
examples/C/inline/inline
examples/C/mcmodel/mcmodel_medany
examples/C/mcmodel/mcmodel_medlow
examples/C/sum/sum
examples/C/sum_mixed/sum_mixed
examples/asm/sumtest/sumtest
examples/asm/example/example
examples/asm/trap/trap
examples/asm/etc/pause

# Other
external
config/deriv
sim/slack-notifier/slack-webhook-url.txt
docs/docker/buildroot-config-src
docs/docker/testvector-generation