16 Commits

Author	SHA1	Message	Date
Ross Thompson	72363f5c66	Added the ability to exclude branch predictor.	2021-04-26 14:27:42 -05:00
Noah Boorstin	6954e6df4c	buildroot: sim is now running! ... yes it only gets through 5 instructions right now. Yes that's my fault.	2021-04-17 14:44:32 -04:00
Domenico Ottolia	92bb38fa8c	Add support for vectored interrupts	2021-04-15 19:13:42 -04:00
Shreya Sanghai	0369fc5d1e	Cherry Pick merge of Shreya's localhistory predictor changes into main. ... fixed minor bugs in localHistory	2021-04-15 09:04:36 -05:00
Thomas Fleming	7126ab7864	Complete basic page table walker	2021-03-30 22:19:27 -04:00
bbracker	11d4a8ab34	first pass at PLIC interface	2021-03-22 10:14:21 -04:00
Shreya Sanghai	bbe0957df5	Merge branch 'gshare' into main ... Conflicts: wally-pipelined/regression/wave.do	2021-03-18 17:25:48 -04:00
Ross Thompson	1091dd10c1	Switched to gshare from global history. ... Fixed a few minor bugs.	2021-03-18 16:05:59 -05:00
Noah Boorstin	bc1a0c6ee7	change ifndef to generate/if	2021-03-18 12:50:19 -04:00
Noah Boorstin	a2b0af460e	everyone gets a bootram	2021-03-18 12:35:37 -04:00
Shreya Sanghai	36f0631203	added gshare and global history predictor	2021-03-16 17:03:01 -04:00
Shreya Sanghai	9eed875886	added global history branch predictor	2021-03-16 16:06:40 -04:00
Shreya Sanghai	74f1641c5a	Merge branch 'counters' into main ... added a configurable number of performance counters	2021-03-16 11:01:30 -04:00
Ross Thompson	4c8952de6a	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
Shreya Sanghai	f0ec365117	added performance counters	2021-03-04 11:42:52 -05:00
Brett Mathis	79cb7ed571	Parallel FSR's and F CTRL logic	2021-02-04 02:25:55 -06:00