616 Commits

Author	SHA1	Message	Date
David Harris	6d4714651c	Removed more generate statements	2022-01-05 16:25:08 +00:00
David Harris	da5ead23bf	Removed more generate statements	2022-01-05 16:01:03 +00:00
David Harris	d66f7c841b	Removed generate statements	2022-01-05 14:35:25 +00:00
Ross Thompson	98be8201b2	Renamed most signals inside cache.sv so they are agnostic to i or d.	2022-01-04 23:52:42 -06:00
Ross Thompson	fffaf654e6	the i and d caches now share common verilog.	2022-01-04 23:40:37 -06:00
Ross Thompson	13dbf3cc0f	parameterized the caches with the goal of using common rtl for both i and d caches.	2022-01-04 22:40:51 -06:00
Ross Thompson	888a60d8d6	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
Ross Thompson	cb301a78ad	Fixed bug where last line of dcache was not written back to memory on dcache flush.	2022-01-04 21:55:48 -06:00
Ross Thompson	101a8bdb5b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-04 18:41:52 -06:00
Ross Thompson	ecc7bf5237	Fixed dcache flush.	2022-01-04 18:40:58 -06:00
David Harris	9ddc6db0a6	Removed imperas mmu tests; using wallypriv instead	2022-01-04 23:14:53 +00:00
Kip Macsai-Goren	c65fc4d5e6	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 21:30:51 +00:00
Kip Macsai-Goren	46b0cb810d	fixed arch tests to pass make, added 32 bit tests, addded all make-passing tests to tests.vh.	2022-01-04 21:30:38 +00:00
David Harris	0a7ec3e58d	Fixed bad address for F/fmsub_b18-01	2022-01-04 21:04:06 +00:00
David Harris	d1a7416028	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 19:47:51 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00