Kip Macsai-Goren
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0ba1a59a70
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added reset values to stime and stimecmp registers
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2023-03-04 15:06:15 -08:00 |
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Ross Thompson
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7dd8fa16c1
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Renamed BTB misprediction to BTA.
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2023-03-03 00:18:34 -06:00 |
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Ross Thompson
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bdab2c8506
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Added divide cycle counter.
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2023-03-02 23:59:52 -06:00 |
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Ross Thompson
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4b501f6e03
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Added the i and d cache cycle counters.
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2023-03-02 23:54:56 -06:00 |
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Ross Thompson
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b19d51b6a2
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Added fence counter.
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2023-03-02 23:29:20 -06:00 |
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Ross Thompson
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3dbfa96aef
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Added csr write counter, sfence vma counter, interrupt counter, and exception counter.
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2023-03-02 23:21:29 -06:00 |
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Ross Thompson
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cf4d8e6bd0
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Added store stall to performance counters.
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2023-03-02 23:10:54 -06:00 |
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Ross Thompson
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e257ec96ac
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Reordered performance counters and added space for new ones.
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2023-03-02 23:04:31 -06:00 |
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Ross Thompson
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3d1ffac7d7
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Cleaned up branch predictor performance counters.
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2023-03-01 17:05:42 -06:00 |
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Ross Thompson
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2773048bd4
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Name cleanup.
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2023-02-28 17:48:58 -06:00 |
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Ross Thompson
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8af61c0cc0
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Name changes to reflect diagrams.
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2023-02-28 15:37:25 -06:00 |
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Ross Thompson
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bb276da6eb
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Merge branch 'main' of https://github.com/openhwgroup/cvw into main
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2023-02-26 12:06:06 -06:00 |
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David Harris
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d50658addf
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Fixed missing assign when SSTC is not supported
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2023-02-26 07:12:13 -08:00 |
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David Harris
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27acb90217
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Fixed SSTC being unusable in M-MODE without Status.TM. Disable STIMECMP registers when SSTC_SUPPORTED = 0
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2023-02-26 06:30:43 -08:00 |
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Ross Thompson
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e549bec060
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Renamed signals to match new figures.
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2023-02-24 19:51:47 -06:00 |
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David Harris
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bc4410e686
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-02-21 09:58:18 -08:00 |
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David Harris
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0b9fd8a4b3
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Fixed Issue #106: fld rasies load access fault instead of illegal instruction. The IEU controller had considered all fp loads and stores to be legal regardless of whether the FPU is enabled or the type is supported. Merged illegal instruction detection from both units into the Decode stage, saving two bits of pipeline register as well.
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2023-02-21 09:32:17 -08:00 |
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Ross Thompson
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d887124837
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Found a bug where the d and i cache misses were not recorded in the performance counters.
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2023-02-20 16:00:29 -06:00 |
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David Harris
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d83c61cafc
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Added SSTC support for supervisor timer compare, but presently disable support. Reenable for rv32gc and rv64gc after tests pass.
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2023-02-16 07:37:12 -08:00 |
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David Harris
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195e7c1a9c
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Moved STATUS_FS_INT write to if statement to properly prioritize
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2023-02-07 06:55:42 -08:00 |
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David Harris
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0712fa8f67
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Disabled STATUS_FS at reset, fixing issue #71
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2023-02-07 06:31:14 -08:00 |
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David Harris
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d7ae05ae8e
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-02-03 08:36:11 -08:00 |
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David Harris
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99d179dd3e
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Removed pipelined level of hierarchy
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2023-02-02 14:14:11 -08:00 |
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