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Author SHA1 Message Date
David Harris
7fd9b08c12 Merge pull request #234 from AlecVercruysse/cachesim 
CacheSim: Logger improvements, performance logging, sim wrapper
 2023-04-12 03:14:03 -07:00
Limnanthes Serafini
3f9a22e8d4 Minor comments. 2023-04-12 02:57:42 -07:00
David Harris
e6cb928ab2 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-12 02:57:33 -07:00
Limnanthes Serafini
095f3d5542 Added performance and distribution to sim and wrapper. Added colors too! 2023-04-12 02:54:05 -07:00
David Harris
463a1e2b33 Fixed fdivsqrt to avoid going from done to busy without going through idle first 2023-04-12 02:48:40 -07:00
David Harris
bedb3f95eb Swapped in svadu mmu tests 2023-04-12 02:06:52 -07:00
Limnanthes Serafini
65d29306ef Merge branch 'openhwgroup:main' into cachesim 2023-04-12 01:34:45 -07:00
Alec Vercruysse
0ed3e80ee0 only assign ClearDirtyWay for read-write caches 2023-04-12 01:15:35 -07:00
Alec Vercruysse
4cbb9bcec6 refactor cachefsm to get full coverage 
I had to exclude i$ states in coverage-exclusions-rv64gc.do,
but it's referred to by scope, which should be pretty robust
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
a1bbcd5e8a Coverage and readability improvements to LRUUpdate logic 
The genvar stuff was switched to readable names to make it easier
to understand for the first time. In the LRUUpdate logic for loop,
a special case was added for simpler logic in the case of the root
node, to hit coverage.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
5b8c6f070e Make AdrSelMux and CacheBusAdrMux mux2 if READ_ONLY_CACHE 
Some address options are only used in the D$ case.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
7c9f68e984 Remove FlushStage Logic from CacheLRU 
For coverage.

LRUWriteEn is gated by FlushStage in cache.sv,
so removing the signal completely avoids future confusion.

Update cache.sv to reflect cacheLRU edit.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
68a01cb0f8 Exclude (FlushStage & SetValidWay) condition for RO caches 
Spent a long time trying to find a way to see if this condition was
possible, only to become relativly convinced that it isn't.
Basically, since RO cache writes only happen after a long period of
stall for the bus access, there's no way a flushD can be active
at the same time as a RO cache write. TrapM causes a FlushD, but
interrupts are gated by the "commited" logic and the exception
pipeline stalls.

I feel like its worth keeping the logic to be safe
so I've chosen to exclude it rather than explicitely remove it.
 2023-04-12 01:15:35 -07:00
Ross Thompson
18ad6455d0 Merge pull request #232 from stineje/main 
Mod testing for TestFloat
 2023-04-11 23:22:59 -05:00
James Stine
744e170be3 Add feature in testfloat.do to elect wave or nowave 2023-04-11 22:35:04 -05:00
James Stine
811004ef9f Update testbench-fp to run TestFloat for all FP operations 2023-04-11 22:16:20 -05:00
Limnanthes Serafini
a6545a0f47 Logger significantly improved. 2023-04-11 19:29:51 -07:00
Limnanthes Serafini
e5ead0f5b8 Minor logic cleanup (will elaborate in PR) 2023-04-11 19:29:39 -07:00
Limnanthes Serafini
e6a9d236b5 Wrapper for running CacheSim on the rv64gc suites 2023-04-11 19:29:05 -07:00
Limnanthes Serafini
926ec56e18 Cleanup + success message added to CacheSim 2023-04-11 19:28:28 -07:00
David Harris
26fbd3fdb0 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-11 19:08:09 -07:00
David Harris
0eb2511c35 Merge pull request #231 from kipmacsaigoren/priv-tests 
Priv tests Updates for SVADU, and SAIL
 2023-04-11 19:07:13 -07:00
Kip Macsai-Goren
34200e8c76 restored original virt mem tests when svadu is not supported 2023-04-11 18:47:08 -07:00
Kip Macsai-Goren
c4766c8a02 renamed virt mem tests to include svadu 2023-04-11 18:46:37 -07:00
Kip Macsai-Goren
b2d6084eea removed unnecessary 'deadbeef's at the end of reference outputs 2023-04-11 18:32:04 -07:00
Kip Macsai-Goren
a82c0a7780 Modified virt mem tests to do correct r/w when svadu is enabled 2023-04-11 18:08:30 -07:00
Kip Macsai-Goren
4aed880757 enabled SVADU for rv32/64gc 2023-04-11 17:42:26 -07:00
Kip Macsai-Goren
e0b938b409 Removed Trap outputs from writes covered by SVADU 2023-04-11 17:41:57 -07:00
Kip Macsai-Goren
a899606c2b Removed Sail from virt mem tests due to sail not recognizing SVADU 2023-04-11 17:41:31 -07:00
Kip Macsai-Goren
19305fe60a Added sail simulation to priv tests that support it 2023-04-11 13:26:59 -07:00
David Harris
83f5005738 Merge pull request #230 from ACWright256/main 
Excluded coverage for misaligned instructions
 2023-04-11 05:21:09 -07:00
Alexa Wright
fb517163f5 Excluded coverage for misaligned instructions 2023-04-10 23:18:25 -07:00
Noah Limpert
748c8dc234 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-10 19:01:32 -07:00
David Harris
a34867d14e Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic. ImperasDV is happy with these privileged tests now 2023-04-10 07:05:06 -07:00
David Harris
90c9f29beb Merge pull request #226 from SydRiley/main 
Increased coverage for the fpu by adding directed tests to toggle signals
 2023-04-09 21:52:11 -07:00
David Harris
adcc22de9d Merge pull request #223 from ross144/main 
Solves issue 172
 2023-04-09 20:30:26 -07:00
David Harris
23380f343d Merge pull request #224 from kbox13/my-single-change 
Create new PMP tests
 2023-04-09 20:29:03 -07:00
Kevin Box
59e7c9371a Create new pmp tests 
configures all pmpcfg registers in each different address range.
 2023-04-09 16:29:57 -07:00
Noah Limpert
41c79303c6 3rd attempt to resolve conflict in lsu.S file 2023-04-09 15:52:18 -07:00
Sydeny
f4caa62efc Increasing coverage for the fpu by adding directed tests to toggle signals 2023-04-09 13:33:12 -07:00
Ross Thompson
009a020c88 Updated wally figure again to increase resolution. 2023-04-09 12:26:15 -05:00
Ross Thompson
1534ae1879 Updated wally top level figure to fix issue 172. 2023-04-09 12:20:43 -05:00
Ross Thompson
81074a822a Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-09 12:19:44 -05:00
David Harris
c197739841 Merge pull request #222 from kjprime/main 
Remove unnecessary check from compressed instruction decode
 2023-04-09 04:56:21 -07:00
David Harris
df2943b9c1 Merge pull request #221 from dherreravicioso/main 
Added test coverage for Privilege Unit in CSRs
 2023-04-09 04:54:36 -07:00
Kevin Thomas
f7838b869b Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-08 22:56:20 -05:00
Diego Herrera Vicioso
5f9c443781 Added test coverage for floating point registers, some PMP addresses, as well as MTVAL and MCAUSE CSRs. 2023-04-08 16:40:36 -07:00
Ross Thompson
ba08c39eef Merge pull request #220 from davidharrishmc/dev 
Obscure coverage fixes
 2023-04-08 10:27:31 -05:00
David Harris
1c47221983 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-07 21:57:18 -07:00
David Harris
7affe2bdca Waived coverage on BTB memory with byte write enables tied high 2023-04-07 21:56:49 -07:00