Kip Macsai-Goren
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3f4c825a1a
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added mstatus uxl, sxl bit tests (not tested in regression yet)
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2022-09-18 00:11:29 +00:00 |
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Kip Macsai-Goren
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dda3b2d383
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ported endianness tests to 32 bits (not tested in regression yet)
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2022-09-18 00:10:29 +00:00 |
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Kip Macsai-Goren
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99596fac84
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Fixed typos in existing endianness test
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2022-09-18 00:09:52 +00:00 |
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Kip Macsai-Goren
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657e19df08
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added full coverage of subword loads and stores to endianness test
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2022-09-17 23:14:38 +00:00 |
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Kip Macsai-Goren
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a4fc5d3476
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Created initial endianness tests
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2022-09-16 01:06:26 +00:00 |
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David Harris
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8b8f045491
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Completed PLIC-S tests. Regression working. This completes peripheral tests.
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2022-08-03 09:33:56 -07:00 |
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David Harris
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62252c2167
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Debugging plic-s test
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2022-08-03 13:21:09 +00:00 |
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David Harris
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6ee8036ae7
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plic-s debug
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2022-08-03 12:33:09 +00:00 |
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David Harris
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e3ea86f984
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Started plic-s tests
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2022-08-03 03:48:08 +00:00 |
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David Harris
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d2de84a456
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Added parity and stop bit tests to UART
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2022-07-28 04:35:51 +00:00 |
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David Harris
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763a6d7340
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Fixed UART reference output
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2022-07-27 22:16:38 +00:00 |
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David Harris
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f61f0645fe
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Finished UART test
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2022-07-27 04:06:59 +00:00 |
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David Harris
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da275e3c26
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Increased timeout threshold to avoid timeout building riscof tests on slow machine
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2022-07-27 04:05:21 +00:00 |
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slmnemo
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a32698811d
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Updated reference file for UART test
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2022-07-26 09:39:31 -07:00 |
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slmnemo
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8141530f10
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-26 09:15:20 -07:00 |
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slmnemo
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528dfd9170
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Committing changes made to UART test
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2022-07-26 09:14:40 -07:00 |
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David Harris
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449c80b5f7
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More work toward riscof tests
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2022-07-26 06:19:13 -07:00 |
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David Harris
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539174f6f6
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Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd
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2022-07-25 16:23:10 -07:00 |
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David Harris
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55ab81e37b
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More riscof makefile tuning
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2022-07-25 21:15:56 +00:00 |
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David Harris
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6b172723bd
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Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings
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2022-07-25 20:50:38 +00:00 |
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slmnemo
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5b71ceac5c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-22 17:13:38 -07:00 |
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slmnemo
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0bfc3fda1b
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Fixed UART FIFO bugs and added FIFO tests
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2022-07-22 17:13:19 -07:00 |
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Daniel Torres
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b726b05d61
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fixed wally rv32e tests, updated regression makefile to new testflow
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2022-07-22 17:09:46 -07:00 |
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Daniel Torres
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e02c67ed5e
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fixed 32priv tests, now passing
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2022-07-22 15:35:20 -07:00 |
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Daniel Torres
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d95b266d49
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changes to test.vh for compatability
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2022-07-22 15:00:48 -07:00 |
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Daniel Torres
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2bbfd67082
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added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
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2022-07-22 14:58:55 -07:00 |
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slmnemo
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840c40a7ab
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UART updates and PMA fix
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2022-07-22 14:49:03 -07:00 |
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slmnemo
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6d8988f71f
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Added test comments to reference output
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2022-07-22 12:35:59 -07:00 |
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Daniel Torres
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5d7171f6f8
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-22 11:16:09 -07:00 |
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Daniel Torres
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526f70e772
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commiting current changes to riscof wally tests
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2022-07-22 11:14:04 -07:00 |
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slmnemo
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12c92a05ff
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Added new PLIC and UART tests
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2022-07-22 07:12:55 -07:00 |
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slmnemo
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49565f944c
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Added PLIC and UART tests and new functions to the test library
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2022-07-22 07:10:39 -07:00 |
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Daniel Torres
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bd918d37ba
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added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64
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2022-07-21 20:58:58 -07:00 |
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Daniel Torres
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d44ec059d0
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made makefile more specific, just incase future additions
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2022-07-21 12:50:02 -07:00 |
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Daniel Torres
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6e9b4f4075
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removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes
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2022-07-21 12:47:51 -07:00 |
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slmnemo
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77f7b179ee
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fixed GPIO test by adding a new function to clear PLIC interrupts
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2022-07-19 08:59:16 -07:00 |
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Daniel Torres
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c65aa54a1e
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-18 12:13:48 -07:00 |
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Daniel Torres
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3f5a5e1093
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added the sail change to spike to let it all run normally
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2022-07-18 12:13:15 -07:00 |
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Katherine Parry
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8506d2be4c
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fixed uncommented line in makefile
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2022-07-14 00:01:07 +00:00 |
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Katherine Parry
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452b017f9a
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found the bug in the store modification
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2022-07-12 22:42:19 +00:00 |
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Katherine Parry
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2ada8a8bc1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-12 22:37:20 +00:00 |
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Katherine Parry
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cd53ae67d9
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moved fpu ieu write data mux to lsu
|
2022-07-08 23:56:57 +00:00 |
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slmnemo
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43549b10fb
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Fixed error in gpio test
|
2022-07-08 02:27:16 -07:00 |
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Katherine Parry
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0b40f38f02
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added load and store test
|
2022-07-07 21:48:51 +00:00 |
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slmnemo
|
f8059e9e40
|
Resolved conflicts between different gpio files
|
2022-07-05 18:38:52 -07:00 |
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slmnemo
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b3cd9de9e8
|
Fixed discrepancies between GPIO tests and book and removed extra unused code from CLINT tests.
|
2022-07-05 18:21:17 -07:00 |
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David Harris
|
0232593e88
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Fixed typos in gpio test comments
|
2022-07-05 04:57:42 +00:00 |
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David Harris
|
c830a0baf8
|
fixed tininess detection in TestFloat examples, merged change in WALLY-TEST-LIB
|
2022-07-04 03:21:04 +00:00 |
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slmnemo
|
8cc051915d
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Fixed make error
|
2022-07-01 16:28:29 -07:00 |
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Daniel Torres
|
a384a6465b
|
reverted tests.vh to work on existing flow, added commented out paths to new riscof tests once that build has finished
|
2022-06-29 12:32:30 -07:00 |
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