David Harris
|
f806707cb0
|
Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram
|
2021-07-08 16:58:11 -04:00 |
|
David Harris
|
b1592a0542
|
TLB cleanup to match diagrams
|
2021-07-08 16:52:06 -04:00 |
|
David Harris
|
dc44ca4b0b
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-07 06:32:29 -04:00 |
|
David Harris
|
6dc49dd073
|
Renamed tlb ReadLines to Matches
|
2021-07-07 06:32:26 -04:00 |
|
Abe
|
244e197348
|
Changed SvMode to SVMode on line 76
|
2021-07-06 23:28:58 -04:00 |
|
David Harris
|
1301f4df7f
|
Added ASID matching for CAM
|
2021-07-06 18:56:25 -04:00 |
|
Kip Macsai-Goren
|
1652e09b38
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-06 18:54:41 -04:00 |
|
David Harris
|
2b26bbbbd7
|
more TLB name touchups
|
2021-07-06 18:39:30 -04:00 |
|
Kip Macsai-Goren
|
8dfa28125f
|
fixed upper bits page fault signal
|
2021-07-06 18:32:47 -04:00 |
|
David Harris
|
73024fee2d
|
connected signals in tlb by name instead of .*
|
2021-07-06 17:22:10 -04:00 |
|
David Harris
|
18f4fa600a
|
changed tlbphysicalpagemask to structural
|
2021-07-06 17:16:58 -04:00 |
|
David Harris
|
404ba5988a
|
changed tlbphysicalpagemask to structural
|
2021-07-06 17:08:04 -04:00 |
|
David Harris
|
78850bfcd8
|
MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB
|
2021-07-06 15:29:42 -04:00 |
|
Ross Thompson
|
d85bf23af3
|
Merged several of the load/store/instruction access faults inside the mmu.
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
|
2021-07-06 13:43:53 -05:00 |
|
David Harris
|
4c2cbe3200
|
Cleaned up tlb output muxing
|
2021-07-06 10:44:05 -04:00 |
|
David Harris
|
087bed3b67
|
Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines
|
2021-07-06 10:38:30 -04:00 |
|
David Harris
|
69c0358ffd
|
Created tlbcontrol module to hide details
|
2021-07-06 03:25:11 -04:00 |
|
David Harris
|
3cb9e5acd3
|
Fixed adrdecs to use Access signals for TIMs
|
2021-07-05 23:42:58 -04:00 |
|
David Harris
|
a390736f26
|
Don't generate HPTW when MEM_VIRTMEM=0
|
2021-07-05 23:35:44 -04:00 |
|
David Harris
|
e3f6758265
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-05 23:23:17 -04:00 |
|
David Harris
|
8ca7abaa02
|
Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0
|
2021-07-05 20:35:31 -04:00 |
|
Ross Thompson
|
4d9b87a823
|
Fixed combo loop in the page table walker.
|
2021-07-05 16:37:26 -05:00 |
|
Ross Thompson
|
59913e13aa
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-07-05 16:07:27 -05:00 |
|
David Harris
|
57e1111df3
|
Gave names to for loops in generate blocks for ease of reference
|
2021-07-04 18:52:16 -04:00 |
|
David Harris
|
cc04009f82
|
Touched up TLB D and A bit checks
|
2021-07-04 18:17:09 -04:00 |
|
Ross Thompson
|
058c37b5b1
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-07-04 17:07:57 -05:00 |
|
David Harris
|
595df47a3e
|
Fixed TLB_ENTRIES merge conflict and handling of global PTEs
|
2021-07-04 18:05:22 -04:00 |
|
Ross Thompson
|
e198f348da
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-07-04 16:54:31 -05:00 |
|
David Harris
|
71268cc0e8
|
Added ASID & Global PTE handling to TLB CAM
|
2021-07-04 17:53:08 -04:00 |
|
David Harris
|
6b9cfe90d8
|
Added ASID & Global PTE handling to TLB CAM
|
2021-07-04 17:52:00 -04:00 |
|
Ross Thompson
|
f2c4df0a5b
|
Removed the TranslationVAdrQ as it is not necessary.
|
2021-07-04 16:49:34 -05:00 |
|
Ross Thompson
|
8e48865140
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-07-04 16:19:39 -05:00 |
|
David Harris
|
d138d6545d
|
Restructured TLB Read as AND-OR operation with one-hot match/read line
|
2021-07-04 17:01:22 -04:00 |
|
David Harris
|
b59213c83f
|
Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders
|
2021-07-04 16:33:13 -04:00 |
|
David Harris
|
deae60eb1d
|
TLB cleanup
|
2021-07-04 14:59:04 -04:00 |
|
David Harris
|
243c03f870
|
TLB cleanup
|
2021-07-04 14:37:53 -04:00 |
|
David Harris
|
fed096407b
|
TLB minor organization
|
2021-07-04 14:30:56 -04:00 |
|
David Harris
|
a5c0dc8c81
|
Fixed MPRV and MXR checks in TLB
|
2021-07-04 13:20:29 -04:00 |
|
David Harris
|
5b891e05ac
|
TLB mux and swizzling cleanup
|
2021-07-04 12:53:52 -04:00 |
|
David Harris
|
622060b99f
|
Replaced generates with arrays in TLB
|
2021-07-04 12:32:27 -04:00 |
|
David Harris
|
b5df9b282d
|
Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries
|
2021-07-04 11:39:59 -04:00 |
|
David Harris
|
9276446797
|
Switched to array notation for pmpchecker
|
2021-07-04 10:51:56 -04:00 |
|
David Harris
|
c897bef8cd
|
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
|
2021-07-04 01:19:38 -04:00 |
|
Ross Thompson
|
9b959715a0
|
removed mmustall and finished port annotations on ptw and lsuArb.
|
2021-07-03 16:06:09 -05:00 |
|
David Harris
|
ee605d7550
|
Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker
|
2021-07-03 03:29:33 -04:00 |
|
David Harris
|
d3dedc1637
|
Cleaned up PMA/PMP checker unused code
|
2021-07-03 02:25:31 -04:00 |
|
Ross Thompson
|
16e672ada0
|
Fixed up the physical address generation for 64 bit page table walker.
|
2021-07-02 15:49:32 -05:00 |
|
Ross Thompson
|
a8fbbb0631
|
Fixed up the bit widths on the page table walker for rv32.
|
2021-07-02 15:45:05 -05:00 |
|
Ross Thompson
|
46831035fb
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-07-02 13:56:49 -05:00 |
|
David Harris
|
648c09e5ef
|
Optimized PMP checker logic and added support for configurable number of PMP registers
|
2021-07-02 11:04:13 -04:00 |
|