bbracker
55cf205222
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-24 01:42:41 -04:00
bbracker
b84419ff4e
overhauled linux testbench and spoofed MTTIME interrupt
2021-06-24 01:42:35 -04:00
Kip Macsai-Goren
547bf1d0af
added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day.
2021-06-23 19:59:06 -04:00
Ross Thompson
abe5bc90bf
Partial addition of page table walker arbiter.
2021-06-23 17:03:54 -05:00
Ross Thompson
6134c22aca
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
...
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
Katherine Parry
44af47608c
fpu clean-up
2021-06-23 16:42:40 -04:00
Ross Thompson
d5063bee7d
Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
2021-06-23 15:13:56 -05:00
Ross Thompson
5de7a46237
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-23 09:34:42 -05:00
David Harris
718630c378
Reduced complexity of pmpadrdec
2021-06-23 03:03:52 -04:00
David Harris
4189b2d4a7
Reduced complexity of pmpadrdec
2021-06-23 02:31:50 -04:00
David Harris
1972d83002
Refactored pmachecker to have adrdecs used in uncore
2021-06-23 01:41:00 -04:00
David Harris
6dc54acde8
renamed dmem to lsu and removed adrdec module from pmpadrdec
2021-06-22 23:03:43 -04:00
bbracker
ae0fa90450
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-22 18:28:30 -04:00
bbracker
b43a8885cd
give EBU a dedicated PMA unit as just an address decoder
2021-06-22 18:28:08 -04:00
Ross Thompson
e7d8d0b337
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-22 15:47:16 -05:00
Katherine Parry
9eb6eb40bf
rv64f FLW passes imperas tests
2021-06-22 16:36:16 -04:00
Kip Macsai-Goren
d6c5c61b59
Fixed mask assignment error, made usage, variables more clear
2021-06-22 13:31:06 -04:00
Kip Macsai-Goren
b78c09baed
Continued fixing fsm to work right with svmode
2021-06-22 13:29:49 -04:00
Kip Macsai-Goren
852bb9296f
updated so svmode actually causes the right state tranitions. fsm now stuck in idle loop
2021-06-22 11:21:11 -04:00
bbracker
56b0d4d016
added slack notifier for long sims
2021-06-22 08:31:41 -04:00
Ross Thompson
03084a4128
Icache now uses physical lenght bits rather than XLEN.
2021-06-21 16:41:09 -05:00
Ross Thompson
8ec5b0c4f1
Improved some names in icache.
2021-06-21 16:40:37 -05:00
Kip Macsai-Goren
81b433299f
updated mmu test pagetables so that make can be run.
2021-06-21 12:26:47 -04:00
David Harris
82515862e3
Commented out 100k tests to improve speed
2021-06-21 01:43:18 -04:00
David Harris
29ad38fb9e
Added Physical Address and Size to PMA Checker/MMU
2021-06-21 01:27:02 -04:00
David Harris
aef408af58
Reversed [0:...] with [...:0] in bus widths across the project
2021-06-21 01:17:08 -04:00
David Harris
0a59b006ab
Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals
2021-06-20 22:59:04 -04:00
bbracker
83a1f29c37
remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
2021-06-20 22:38:25 -04:00
bbracker
5afad80432
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-20 22:29:40 -04:00
bbracker
665a67f442
linux actually uses FPU now!
2021-06-20 22:29:21 -04:00
Katherine Parry
26bad083ad
all rv64f instructions except convert, divide, square root, and FLD pass
2021-06-20 20:24:09 -04:00
bbracker
1f2a967e0f
read from MSTATUS workaround because QEMU has incorrect MSTATUS
2021-06-20 10:11:39 -04:00
bbracker
2611d214a6
testbench update b/c QEMU extends 32b CSRs to 64b
2021-06-20 09:24:19 -04:00
bbracker
7aa2f0d953
make xCOUNTEREN what buildroot expects it to be
2021-06-20 09:22:31 -04:00
bbracker
6e9c6e3e6a
whoops wavedo typo
2021-06-20 05:36:54 -04:00
bbracker
9469367da3
make buildroot ignore SSTATUS because QEMU did not originally log it
2021-06-20 05:31:24 -04:00
bbracker
78f4703dc9
MSTATUS workaround
2021-06-20 04:48:09 -04:00
bbracker
927d99cf3b
workaround for ignoring MTIME
2021-06-20 02:26:39 -04:00
bbracker
52fb630379
remove lingering busybear stuff from buildroot do files
2021-06-20 00:50:53 -04:00
bbracker
124ef980e3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-20 00:40:44 -04:00
bbracker
3e32ba3684
make buildroot waves only turn on after a user-specified point
2021-06-20 00:39:30 -04:00
Ross Thompson
bb756849a7
Revert "Icache now uses physical lenght bits rather than XLEN."
...
This reverts commit d4de8a54a2
2021-06-19 08:58:34 -05:00
Ross Thompson
e4c932265d
Revert "Improved some names in icache."
...
This reverts commit 22ea801edb
2021-06-19 08:58:32 -05:00
bbracker
ebe893b70c
change buildroot config to use relative path for testvectors
2021-06-18 22:28:07 -04:00
bracker
3d99c9c2c4
gitignore merge
2021-06-18 21:12:05 -05:00
bracker
ed75172f21
handle tera usernames more gracefully
2021-06-18 21:11:14 -05:00
bbracker
10ca2ac5bc
on-Tera solution for sym linking to linux testvectors
2021-06-18 22:01:18 -04:00
bracker
a9f9ef1180
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-18 20:41:01 -05:00
bracker
8a8b0dcfd7
script support for copying large files from tera
2021-06-18 20:40:19 -05:00
Kip Macsai-Goren
20c8e6d929
fixed trap handler, maker errors, pagetables still need work.
2021-06-18 18:13:08 -04:00
