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Author SHA1 Message Date
bbracker
44a48cf28d organize linux-testgen folder, add readme to describe Buildroot process, add Buildroot config source files 2021-07-08 19:18:11 -04:00
Ross Thompson
94c3fde724 Renamed signal in LSU toLSU and fromLSU to toDCache and fromDCache. 2021-07-08 18:03:52 -05:00
Ross Thompson
93aa39ca31 completed read miss branch through dcache fsm. 
The challenge now is to connect to ahb and lsu.
 2021-07-08 17:53:08 -05:00
David Harris
4f1a85ca7c Eliminate reserved bits from TLB RAM 2021-07-08 17:35:00 -04:00
David Harris
38772de21f Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram 2021-07-08 16:58:11 -04:00
David Harris
1190729896 TLB cleanup to match diagrams 2021-07-08 16:52:06 -04:00
Ross Thompson
910ddb83ae This d cache fsm is getting complex. 2021-07-08 15:26:16 -05:00
Ross Thompson
1fe06bc670 Partial implementation of the data cache. Missing the fsm. 2021-07-07 17:52:16 -05:00
David Harris
5d5274ec73 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-07 06:32:29 -04:00
David Harris
2bab3f769b Renamed tlb ReadLines to Matches 2021-07-07 06:32:26 -04:00
Abe
84711fbdc8 Updated MISA defining as well as porting sizes for peripherals (34 to 56) 2021-07-07 02:37:09 -04:00
Abe
c721341691 Commented out printf statements for quicker simulation time. Also added function minstretDiff, which calculates the number of machine instructions retired during the coremark benchmark's runtime, excluding setup time. 2021-07-07 02:28:11 -04:00
Abe
b536065ee8 Removed debugging loop to test timers for clarity 2021-07-06 23:37:43 -04:00
Abe
8dc40e988e Updated portme file to include counters MTIME and MINSTRET. Timer currently set to read milliseconds running at 100MHZ, but this can be changed by setting a different clock speed in the testbench sv file and manipulating TIMER_RES_DIVIDER on line 120 2021-07-06 23:35:47 -04:00
Abe
b757c96b2d Changed SvMode to SVMode on line 76 2021-07-06 23:28:58 -04:00
David Harris
af619dcd75 Added ASID matching for CAM 2021-07-06 18:56:25 -04:00
Kip Macsai-Goren
8350622f65 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 18:54:41 -04:00
David Harris
7d857cf4bd more TLB name touchups 2021-07-06 18:39:30 -04:00
Kip Macsai-Goren
e08a578908 fixed upper bits page fault signal 2021-07-06 18:32:47 -04:00
David Harris
2e2aa2a972 connected signals in tlb by name instead of .* 2021-07-06 17:22:10 -04:00
David Harris
ee3a321002 changed tlbphysicalpagemask to structural 2021-07-06 17:16:58 -04:00
David Harris
f960561cbb changed tlbphysicalpagemask to structural 2021-07-06 17:08:04 -04:00
David Harris
fd0cd930a7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 15:29:49 -04:00
David Harris
032c38b7e7 MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB 2021-07-06 15:29:42 -04:00
Kip Macsai-Goren
757e4f3b54 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 15:05:51 -04:00
Ross Thompson
412691df2d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-06 13:45:20 -05:00
Ross Thompson
3345ed7ff4 Merged several of the load/store/instruction access faults inside the mmu. 
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
 2021-07-06 13:43:53 -05:00
bbracker
d3dd70e3e6 more completely uncomment MMU tests to make sim wally work 2021-07-06 14:33:52 -04:00
Kip Macsai-Goren
137145144f edited tests so regression would pass with float enabled. this IS NOT a comprehensive test for fs yet 2021-07-06 14:28:26 -04:00
Abe
8854532a79 Disabled MCOUNTINHIBIT to enable csr counters (changed to 32'h0 on line 140) 2021-07-06 12:37:58 -04:00
Ross Thompson
7af8cfba18 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-06 10:41:45 -05:00
Ross Thompson
6e7e318396 Fixed bug in the LSU pagetable walker interlock. 2021-07-06 10:41:36 -05:00
David Harris
b4082ba776 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 10:44:17 -04:00
David Harris
30fdd7abc8 Cleaned up tlb output muxing 2021-07-06 10:44:05 -04:00
David Harris
d58cad89a8 Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines 2021-07-06 10:38:30 -04:00
Kip Macsai-Goren
7e9961cac4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 10:16:34 -04:00
David Harris
694badcc6b Created tlbcontrol module to hide details 2021-07-06 03:25:11 -04:00
David Harris
f805aea236 Implemented TSR, TW, TVM, MXR status bits 2021-07-06 01:32:05 -04:00
David Harris
8b23162d6d Fixed adrdecs to use Access signals for TIMs 2021-07-05 23:42:58 -04:00
David Harris
71711c54c9 Don't generate HPTW when MEM_VIRTMEM=0 2021-07-05 23:35:44 -04:00
David Harris
179c8d3ed4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-05 23:23:17 -04:00
David Harris
6bac566bb7 Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0 2021-07-05 20:35:31 -04:00
Ross Thompson
530ddd667b Fixed combo loop in the page table walker. 2021-07-05 16:37:26 -05:00
Ross Thompson
2a62ee2e70 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-05 16:07:27 -05:00
Kip Macsai-Goren
20cd0e208b added new mmu tests to makefrag and commented out in the testbench 2021-07-05 10:54:30 -04:00
Kip Macsai-Goren
97b0c8f368 added final mmu test that passes make. They still don't pass simulation. 2021-07-05 10:49:23 -04:00
Kip Macsai-Goren
ec1df3f1e8 cleaned up comments, minor edits 2021-07-05 10:47:20 -04:00
Kip Macsai-Goren
71978a144e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-05 10:45:44 -04:00
David Harris
5f91b339aa Added F_SUPPORTED flag to disable floating point unit when not in MISA 2021-07-05 10:30:46 -04:00
David Harris
ac163e091c Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported 2021-07-04 19:33:46 -04:00