David Harris
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2b241f8bbd
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Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding
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2022-08-26 21:18:18 -07:00 |
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David Harris
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812158aeee
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Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each
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2022-08-26 20:26:12 -07:00 |
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David Harris
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95dd50a567
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Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem
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2022-08-26 20:12:03 -07:00 |
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Ross Thompson
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e605ef57dc
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BROKEN. Don't use this commit.
Issue running cacheless with bus.
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2022-08-25 11:02:46 -05:00 |
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Ross Thompson
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769af32f2a
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Renamed RAM to UNCORE_RAM.
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2022-08-24 18:09:07 -05:00 |
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Ross Thompson
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51adf6cba9
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Modified the lsu/ifu memory configurations.
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2022-08-24 12:35:15 -05:00 |
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Ross Thompson
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69d520a7eb
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Removed replay from the config files.
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2022-07-24 00:34:11 -05:00 |
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slmnemo
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528869ef14
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Removed references to initialization files
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2022-06-23 16:50:27 -07:00 |
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DTowersM
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4e5d7ec3d6
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changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability
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2022-06-10 00:37:53 +00:00 |
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slmnemo
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35caa03e46
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Updated Linux testbench to use new force/unforce method for Branch predictor init and removed related .txt files
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2022-06-02 02:51:51 +00:00 |
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David Harris
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8066ba45e8
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Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
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2022-05-08 06:46:35 +00:00 |
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Kip Macsai-Goren
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3d1e1202f3
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set WFI timeout to after 16 bits of counting for all configs
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2022-04-28 18:14:08 +00:00 |
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Shreya Sanghai
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c3164f0ce1
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added bpred size to wally config
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2022-04-18 04:21:03 +00:00 |
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David Harris
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2436534687
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First implementation of WFI timeout wait
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2022-04-17 17:20:35 +00:00 |
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Katherine Parry
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20885f4dea
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generating all testfloat vectors
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2022-04-04 17:17:12 +00:00 |
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Ross Thompson
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e802deb4d6
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Can now support the following memory and bus configurations.
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
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2022-03-11 15:18:56 -06:00 |
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bbracker
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6caa97bb26
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change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
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2022-02-22 03:46:08 +00:00 |
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Ross Thompson
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6cd9d84e7f
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New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
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2022-02-17 17:19:41 -06:00 |
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Ross Thompson
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13561c67bd
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-02-08 14:22:19 -06:00 |
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David Harris
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c07584bb70
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rv32e config update
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2022-02-08 17:59:50 +00:00 |
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Ross Thompson
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c2377eaaf4
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-02-08 11:36:30 -06:00 |
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Ross Thompson
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3cd067ac6a
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Finished merge.
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2022-02-08 11:36:24 -06:00 |
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David Harris
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9ad3f26365
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Restored E tests to makefrag
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2022-02-08 16:41:11 +00:00 |
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David Harris
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096242a6d8
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Merged TIM and regular testbenches. RV32e now working and back in regression.
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2022-02-08 12:18:13 +00:00 |
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David Harris
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0dd8c719ad
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Modified regression to use proper rv32e test name, but rv32e_wally32e still isn't passing due to loop exceeding iteration limit
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2022-02-05 05:35:51 +00:00 |
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David Harris
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23868a33bc
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Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
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2022-02-05 04:16:18 +00:00 |
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David Harris
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14c1d86953
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rv32e
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2022-02-04 01:56:30 +00:00 |
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David Harris
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761dae72fe
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Config file & wally-riscv-arch-test cleanup
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2022-02-02 16:35:52 +00:00 |
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David Harris
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c6adb7b6b1
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Updated configs to fix GPIO address to match FU540
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2022-01-26 18:16:34 +00:00 |
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David Harris
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5842d780a7
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Defined rv32e and rv32emc configs
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2022-01-17 14:01:01 +00:00 |
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