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211 Commits

Author SHA1 Message Date
Ross Thompson
f30c92e82a Added wfi and interrupt to tracer. 2023-07-11 15:09:04 -05:00
Ross Thompson
b26dc6db7f Simplificaiton of function tracker. 2023-07-11 10:51:17 -05:00
Ross Thompson
74834bde2c Removed duplicate signal name from testbench. 2023-07-07 16:34:08 -05:00
Ross Thompson
0394f3232f Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-06 14:55:43 -05:00
David Harris
34ce25ca81 Commented SVADU requirements for wally32priv mmu tests 2023-07-04 11:34:07 -07:00
David Harris
4c921fc797 Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder 2023-07-02 13:29:27 -07:00
James E. Stine
407bf44548 Modification (temporary) to testbench-fp.sv to allow testing of anything FMA. This might need to be changed with OpCtrl to make more robust for future expansion. 2023-06-29 08:46:11 -05:00
James E. Stine
012316aa94 Minor tweak to fix vectors not working for fadd. 2023-06-26 14:25:44 -05:00
James E. Stine
83a79b3a40 Fix items related to testing of TestFloat that were not always matching. The issue resulted due to the repeat statement that interferes with the always block. I separated the two to allow them to work correctly 2023-06-26 10:14:49 -05:00
James E. Stine
e913c1ea46 Modify testbench-fp.sv to handle parameterization as well some other minor mods. Have to make a better FPUActive desgination but for now works 2023-06-22 15:27:17 -05:00
James E. Stine
394c7ac9af Update sim-testfloat to fix errors due to bad config element. I am not sure of the reasoning, but the specific path to the testvector was not getting inserted in Questa. This modification also adds features to test individualized tests (.e.g, binary16 only) -- documentation is added in the FPbuild.txt file 2023-06-20 17:26:54 -05:00
Ross Thompson
626a918668 FPGA updates. 2023-06-20 11:11:34 -05:00
Ross Thompson
1d2eb60ffb Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-18 16:37:19 -05:00
David Harris
60931e7d5c Fixed embench to run all tests, even ones not in 1.0 2023-06-17 20:38:51 -07:00
David Harris
e2f927b4e6 Replaced zext.h with zext.h_64 in rv64 tests because old one is obsolete 2023-06-16 16:07:28 -07:00
Ross Thompson
4bee446cad Vivado requires an intermediate wrapper file for parameterization. 2023-06-16 16:30:14 -05:00
David Harris
dfedc13cfc erge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-16 10:32:37 -07:00
David Harris
281c036e70
Merge pull request #342 from ross144/main 
Testbench generates embench output files
 2023-06-16 10:32:18 -07:00
Ross Thompson
509aee36ef Modified the testbench to generate the required files for embench scripts. 2023-06-16 12:27:22 -05:00
David Harris
2d94800ad7 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-16 10:03:48 -07:00
David Harris
1cb0cf38b4
Merge pull request #341 from ross144/main 
Fix embench so it does not crash
 2023-06-16 10:03:41 -07:00
Ross Thompson
3f628d6bf2 embench testbench no longer crashes. 2023-06-16 11:54:41 -05:00
David Harris
3c98ed9e29 Added assertions for ZICNTR and ZIHPM 2023-06-16 09:26:02 -07:00
eroom1966
9125f25880 add changes for latest IDV file layout 2023-06-16 16:43:53 +01:00
Ross Thompson
605ddf7990 Fixed the imperas testbench to work with parameters. 2023-06-16 08:59:52 -05:00
Ross Thompson
110a41c046 Have the linux testbench working in the mean time. Before the consolidation. 2023-06-15 16:18:37 -05:00
Ross Thompson
34d1d50b87 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 15:38:38 -05:00
Ross Thompson
a011b7d591 Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
a55bcad5c1 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 14:57:23 -05:00
Ross Thompson
3c4677ef63 Major cleanup of testbench. 2023-06-15 14:57:05 -05:00
Ross Thompson
44c72c20e2 Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems. 2023-06-15 14:05:44 -05:00
Ross Thompson
e431f90cf3 Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
David Harris
bcb9c242d4 Added BMU instructions to instruction name decoder 2023-06-15 09:26:09 -07:00
Ross Thompson
d79c084a70 Significant refactoring of testbench. 2023-06-14 17:02:49 -05:00
Ross Thompson
7ac5239d6a Removed old configs from function name module. 2023-06-14 16:35:55 -05:00
Ross Thompson
19b7819d53 Found and fixed the source of the new testbench slow down. I accidentally increased the size of the signature buffer by 10x. 2023-06-14 14:11:25 -05:00
Ross Thompson
7fb58f5cac more testbench improvements. 2023-06-14 12:23:26 -05:00
Ross Thompson
8caa4dfcfb Continued improvements to testbench. 2023-06-14 12:11:55 -05:00
Ross Thompson
005307fc16 Resolved the duplicated check signature issue. 2023-06-14 11:50:12 -05:00
Ross Thompson
5d0e86f650 Fixed another issue with the timing of memory resets in the new testbench. 2023-06-13 16:24:38 -05:00
Ross Thompson
ed7d785175 Now have most of the regression tests running again. 2023-06-13 15:09:40 -05:00
Ross Thompson
5b0467b287 Cleaned up testbench more. 2023-06-13 14:05:17 -05:00
Ross Thompson
7d53af9206 Compacted memory resets. 2023-06-13 13:57:58 -05:00
Ross Thompson
269d7b2430 More cleanup. 2023-06-13 13:54:07 -05:00
Ross Thompson
40f7031fe7 Fixed the multliple reads of the same preload memory file. 2023-06-13 13:52:02 -05:00
Ross Thompson
261b34af5d The testbench now at least runs the arch64i in rv64gc config. Still has several issues 
1. need to remove all dead code
2. seems to still be double reading memory files sometimes.
3. batch mode does not work.
 2023-06-13 13:18:46 -05:00
David Harris
b83d483c9d
Revert "Update for new layout of ImperasDV files" 2023-06-13 04:17:56 -07:00
Ross Thompson
d9f7daf5e0 The new testbench is almost working except the shadow copy is not working. 2023-06-12 15:08:23 -05:00
Ross Thompson
80a6170fe1 Progress towards new testbench. 2023-06-12 14:06:17 -05:00
Ross Thompson
bbe3f1caf0 Created temporary wrapper for lint. 2023-06-12 11:49:51 -05:00