Ross Thompson
f2c1ca4bd5
added support to due partial fpga simulation.
2021-09-26 15:00:00 -05:00
Ross Thompson
6dc25e07c2
Updated the fpga bios code to emulate the same behavior as qemu's bootloader and it also copies
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the flash card to dram.
Fixed latch issue in the sd card reader.
2021-09-26 13:22:23 -05:00
Ross Thompson
8e29d4472e
GPIO marker to indicate the sdc to dram transfer complete.
2021-09-25 19:29:15 -05:00
Ross Thompson
5bdd6a9d0c
Almost done writting driver for flash card reader.
2021-09-25 19:05:07 -05:00
Ross Thompson
3a15cc7872
We now have a rough sdc read routine.
2021-09-25 17:51:38 -05:00
Ross Thompson
dd9fe60b28
Write of the SDC address register is correct. The command register is not yet working.
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The root problem is the command register needs to be reset at the end of the SDC transaction.
2021-09-24 18:48:11 -05:00
Ross Thompson
5663522a3f
Now have software interacting with the initialization and settting the address register.
2021-09-24 18:30:26 -05:00
Ross Thompson
232d4a554f
Have program which checks for sdc init and issues read, but read done is
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not correctly being read back by the software. The error is in how the
sdc indicates busy.
2021-09-24 15:53:38 -05:00
Ross Thompson
144003cb41
FPGA test bench and test program.
2021-09-12 20:41:54 -05:00
Ross Thompson
b739853784
Added special tests for checking the accuracy of global and gshare branch
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predictors.
2021-06-04 11:01:54 -05:00
Ross Thompson
976b612992
updated isa extensions for simple branch predictor test.
2021-06-04 10:41:32 -05:00
Ross Thompson
5bc2a8b346
Now have global history working correctly.
2021-06-01 10:57:43 -05:00
Ross Thompson
1db8d0e59c
may have fixed the global branch history predictor.
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The solution required a completed rewrite and understanding of how the GHR needs to be speculatively updated and repaired.
2021-05-31 16:11:12 -05:00
Ross Thompson
668a79cf77
Updated benchmarking code.
2021-05-27 11:48:29 -05:00
Ross Thompson
daf344f1ba
Updated branch predictor tests/benchmarks.
2021-05-24 11:13:33 -05:00
Ross Thompson
75b97f1422
Created special test for driving the instruction spill error.
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The extact problem occurs when a 4 byte instruction startles two cache blocks (or without a cache two ahbi words) and the code jumps to a cache block other than the next cache block. Consider the following sample of code.
0000000000000080 <test_spill>:
80: 42a9 li t0,10
82: 0001 nop
84: 0001 nop
86: 0001 nop
88: 02bd addi t0,t0,15
8a: 00628e33 add t3,t0,t1
8e: 01ce8963 beq t4,t3,a0 <match>
0000000000000092 <failure>:
92: 557d li a0,-1
94: 8082 ret
96: 00000013 nop
9a: 00000013 nop
9e: 0001 nop
00000000000000a0 <match>:
a0: 1ffd addi t6,t6,-1
a2: fc0f9fe3 bnez t6,80 <test_spill>
a6: 4501 li a0,0
a8: 8082 ret
Instructions 0x88, 0x8a and 0x8e are read incorrectly. However once the branch predictor begins to correctly predict the beq at 0x8e the instrution at 0xa0 is loaded incorrectly as the 2 upper bytes of 0x8e and the two bytes of 0x92. This amalgamation causes c.addi at 0xa0 to do something else and the loop never terminates.
The button of wavefile wave.do shows the exact problem in the 'icache'.
2021-04-08 15:05:08 -05:00
Ross Thompson
7f12c7af90
Switch to use RV64IC for the benchmarks.
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Still not working correctly with the icache.
instr
addr correct got
2021-04-07 19:12:43 -05:00
Ross Thompson
0a20e33971
Steps to getting branch predictor benchmarks running.
2021-04-06 21:20:51 -05:00
Ross Thompson
cdb7d15709
Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.
2021-03-24 15:56:55 -05:00
Ross Thompson
58487db60a
Edited sieve to work with wally. It was using the time of day to compute runspeed; however this functionality does not yet work in the wally software stack.
2021-03-24 09:22:21 -05:00
Ross Thompson
c7e34bd4a0
added a whole bunch of interseting test code for branches which does not work.
2021-03-23 13:54:59 -05:00
