15 Commits

Author	SHA1	Message	Date
David Harris	f16267ddbc	uncore cleanup	2023-01-14 17:00:58 -08:00
David Harris	1ec42b9d50	sdc cleanup	2023-01-14 16:49:44 -08:00
David Harris	3ad4ae352c	uncore cleanup	2023-01-14 06:15:35 -08:00
David Harris	8c6ddcc15b	changed name to CORE-V-WALLY	2023-01-11 15:15:08 -08:00
David Harris	3ea4dd4898	Changed Wally to CORE-V Wally	2023-01-11 14:03:44 -08:00
David Harris	739c2c8322	Changed MIT license to Solderpad License	2023-01-10 11:35:20 -08:00
David Harris	33c910f952	Remove unused signals	2023-01-07 06:26:29 -08:00
Ross Thompson	c636387613	Merged testbench-fpga into testbench. ... Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.	2022-08-24 17:52:25 -05:00
David Harris	381f3298d8	Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc	2022-07-08 09:09:02 +00:00
Ross Thompson	077beb18dd	Constraint changes for 40Mhz wally.	2022-04-04 10:50:48 -05:00
Ross Thompson	400b5f7632	Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.	2022-04-04 09:57:26 -05:00
David Harris	120fb7863f	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	fedb9d3287	moved proposed-sdc	2022-01-07 12:44:21 +00:00
David Harris	85fa620cfb	Finished removing generate statements	2022-01-05 16:41:17 +00:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00