Ross Thompson
5b740fbf60
Removed SDC from repo due to copy right issue.
...
Modified fpga build flow to reference it outside the repo.
2023-01-20 14:57:06 -06:00
Jacob Pease
6e7cc5740f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into boot
2023-01-20 14:53:37 -06:00
Ross Thompson
b1f3bd566c
Formatting.
2023-01-20 13:13:05 -06:00
Ross Thompson
f78bfc4940
Formatting.
2023-01-20 13:09:42 -06:00
Ross Thompson
c7f4970597
Formatting.
2023-01-20 13:05:10 -06:00
Ross Thompson
6142c96946
Reformatting cachefsm.
2023-01-20 12:49:55 -06:00
Ross Thompson
7e96f3e8f7
Formatting.
2023-01-20 12:41:57 -06:00
Ross Thompson
95de716a17
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2023-01-20 12:37:12 -06:00
Ross Thompson
b8a699270e
More cleanup and formatting.
2023-01-20 12:34:40 -06:00
David Harris
032332ebae
renamed comparator module
2023-01-20 10:13:47 -08:00
David Harris
1c07eb623d
Updated HMC Synopysys license manager
2023-01-20 10:13:20 -08:00
Ross Thompson
f1049be6c1
More cleanup and formatting.
2023-01-20 12:09:21 -06:00
Ross Thompson
4a2d02ab28
Formatting.
2023-01-20 11:51:10 -06:00
Ross Thompson
11c44006c4
Integrated the missing zifence tests into the regression test.
2023-01-20 10:34:49 -06:00
Ross Thompson
eb19b1b499
Imperas found a bug with the Fence.I instruction.
...
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold. This cause the d$ flush to go high while in ReadHold. The solution is
to ensure the cache continues to assert Stall while in WriteLine state.
There was a second issue also. The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
2023-01-20 10:17:21 -06:00
Ross Thompson
6f3b8680d5
Imperas found a bug with the Fence.I instruction.
...
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold. This cause the d$ flush to go high while in ReadHold. The solution is
to ensure the cache continues to assert Stall while in WriteLine state.
There was a second issue also. The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
2023-01-20 09:41:18 -06:00
Ross Thompson
87c1f285c1
Merge branch 'imperas' of github.com:davidharrishmc/riscv-wally into imperas
2023-01-20 08:38:08 -06:00
Lee Moore
e1e693a1d2
Merge pull request #13 from eroom1966/imperas
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Merge pull request #5 from davidharrishmc/imperas
2023-01-20 14:34:38 +00:00
Lee Moore
cddc111cd6
Merge pull request #5 from davidharrishmc/imperas
...
Merge pull request #12 from eroom1966/imperas
2023-01-20 14:33:21 +00:00
Lee Moore
56eeb7cf9b
Merge pull request #12 from eroom1966/imperas
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Imperas
2023-01-20 14:32:57 +00:00
Lee Moore
3427f7de20
Merge pull request #4 from davidharrishmc/imperas
...
Merge pull request #11 from eroom1966/imperas
2023-01-20 14:32:21 +00:00
eroom1966
70f8c7a14e
Merge branch 'imperas' of https://github.com/eroom1966/riscv-wally into imperas
2023-01-20 14:31:17 +00:00
Jacob Pease
f77fa9fede
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into boot
2023-01-20 06:12:17 -06:00
Ross Thompson
63dbebcb5a
Improved comment.
2023-01-19 17:41:57 -06:00
Ross Thompson
91bd55d9ba
ram uses always rather than always_ff due to modelsim issue.
2023-01-19 17:41:15 -06:00
Ross Thompson
30935fd2b7
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2023-01-19 17:28:53 -06:00
Ross Thompson
78e8598ec8
Added comment about needed changes in BTB.
2023-01-19 17:28:00 -06:00
Ross Thompson
f7b869960a
Rough draft of Install guide.
2023-01-19 17:27:45 -06:00
David Harris
aed6f79d1e
Removed study versions from comparator
2023-01-19 15:13:35 -08:00
David Harris
ad3b528b5d
Moved unused study files to studies directory
2023-01-19 15:13:11 -08:00
Jacob Pease
fbe5c63219
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into boot
2023-01-19 16:59:24 -06:00
Jacob Pease
12b379ebd8
Added IOBUFs to SDCDat. Edited debug2.xdc. Dwidth converter error.
2023-01-19 16:57:43 -06:00
David Harris
264362ce17
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2023-01-19 14:47:54 -08:00
David Harris
a1b25e1039
RAM declaration cleanup:
2023-01-19 14:47:51 -08:00
Ross Thompson
75391f4b56
Formatting.
2023-01-19 15:06:37 -06:00
Ross Thompson
40d62ec0d1
Formatting.
2023-01-19 14:18:46 -06:00
Ross Thompson
999477bb02
Formatting and name changes.
2023-01-19 14:16:29 -06:00
Lee Moore
fe4f8428ca
Merge pull request #11 from eroom1966/imperas
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Imperas
2023-01-19 14:56:44 +00:00
Lee Moore
35a6e407b6
Merge branch 'davidharrishmc:imperas' into imperas
2023-01-19 14:56:18 +00:00
eroom1966
43d5769bd9
update
2023-01-19 13:29:46 +00:00
eroom1966
5212499513
correct the HASH
2023-01-19 10:41:11 +00:00
Lee Moore
e12867af8e
Merge pull request #10 from eroom1966/imperas
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Imperas
2023-01-19 10:28:27 +00:00
Lee Moore
d12758675c
Merge pull request #3 from davidharrishmc/imperas
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Imperas
2023-01-19 10:27:52 +00:00
eroom1966
f9b14ccdc5
customer commands
2023-01-19 10:20:55 +00:00
Ross Thompson
0bbf6e4ae2
Formatting.
2023-01-18 19:26:20 -06:00
Ross Thompson
21b2b10e78
Formatting spillsupport.
2023-01-18 19:25:54 -06:00
Ross Thompson
db48e547f0
Formatting.
2023-01-18 19:11:30 -06:00
Ross Thompson
9170827c98
Reduced complexity of spill logic by ensuring the irom outputs offset instrutions on a spill.
2023-01-18 19:10:34 -06:00
Ross Thompson
e79c403fe1
More IROM cleanup.
2023-01-18 18:47:02 -06:00
Ross Thompson
63577cbf4a
Cleanup dtim and irom.
2023-01-18 18:44:30 -06:00
