Ross Thompson
edc4630742
Formating.
2023-01-18 16:52:46 -06:00
Ross Thompson
32589a5efc
Formating.
2023-01-18 16:47:40 -06:00
Ross Thompson
cd5e62119a
Added commenets and formating to abhcachefsm and abhcacheinterface.
2023-01-17 22:22:23 -06:00
David Harris
17fd2d2a3b
ebu cleanup
2023-01-14 19:19:34 -08:00
David Harris
7d93659f6b
changed name to CORE-V-WALLY
2023-01-11 15:15:08 -08:00
David Harris
b911056e66
Changed Wally to CORE-V Wally
2023-01-11 14:03:44 -08:00
David Harris
e92cffbb5e
Changed MIT license to Solderpad License
2023-01-10 11:35:20 -08:00
David Harris
5fbba604f1
Remove unused CACHE_ENABLED parameter
2023-01-07 09:57:24 -08:00
Ross Thompson
ab3c5a0ca7
Rough draft of cache flush fsm enhancement.
2022-12-16 15:28:22 -06:00
Ross Thompson
6d573b32d2
Changed CPUBusy to Stall in ebu modules.
2022-12-11 15:51:35 -06:00
Ross Thompson
8658a25218
Renamed Word to Beat for ahbcacheinterface.
2022-11-09 17:52:50 -06:00
Ross Thompson
028e2b0f91
Renamed CACHE_EVICT to CACHE_WRITEBACK.
2022-11-09 17:43:06 -06:00
Ross Thompson
be8e0eee1b
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
Ross Thompson
65c2fe294a
Merged cacheable with seluncachedadr.
2022-10-17 13:29:21 -05:00
Ross Thompson
d81af3bca8
Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore.
2022-09-29 11:54:03 -05:00
Ross Thompson
4062fe56c0
Possible fix to the bus cache interaction.
2022-09-27 11:34:33 -05:00
Ross Thompson
0fcc314d06
Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed.
2022-09-26 12:48:26 -05:00
Ross Thompson
38edbde966
Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
...
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
2022-09-23 11:46:53 -05:00
Ross Thompson
2c86badeb2
pipelining of fetch into evict AHB requests.
2022-09-13 17:51:55 -05:00
Ross Thompson
bc15f6c5e4
Added logic to make burst optional.
2022-09-06 09:21:21 -05:00
Ross Thompson
2554f96662
Cleaned up hacks to ram.
2022-09-04 14:52:40 -05:00
Ross Thompson
221367efb9
Disabled AHB burst mode, which discovered a bug.
...
Multimanger bug in how back to back requests were arbitrated.
2022-09-03 22:31:41 -05:00
Ross Thompson
00cffb0aa5
Renamed state in buscachefsm to match AHB phases.
2022-09-02 17:17:40 -05:00
Ross Thompson
6f366c643d
Possible fix for AHB trailing ~HREADY bug.
2022-09-02 16:58:35 -05:00
Ross Thompson
eae56a890c
marked possible improvement to ahb bus fsms.
2022-08-31 23:57:08 -05:00
Ross Thompson
7598fbcb3b
Reduced busfsm to 3 states!
2022-08-31 16:11:59 -05:00
Ross Thompson
12d1ef2144
More renaming.
2022-08-31 14:49:08 -05:00
