Ross Thompson
ea70e1c598
Optimized the ebu's beat counting.
2022-10-05 10:58:23 -05:00
Ross Thompson
e27fcb1577
Added logic to not implement the save/restore muxes for LSU in the EBU's controller input stage.
2022-09-29 18:37:34 -05:00
Ross Thompson
2c0132aa9c
Renamed signals in EBU.
2022-09-29 18:29:38 -05:00
Ross Thompson
58d597b614
Simplification to EBU.
2022-09-29 18:06:34 -05:00
Ross Thompson
d81af3bca8
Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore.
2022-09-29 11:54:03 -05:00
Ross Thompson
32449dfe97
Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.
2022-09-28 17:39:51 -05:00
Ross Thompson
4db017dac3
Possible fix for ifu/lsu arbiration issue.
2022-09-27 17:24:35 -05:00
Ross Thompson
4062fe56c0
Possible fix to the bus cache interaction.
2022-09-27 11:34:33 -05:00
Ross Thompson
996c4ca8f2
renamed ahbmulticontroller to ebu.
2022-09-26 14:37:18 -05:00
Ross Thompson
0fcc314d06
Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed.
2022-09-26 12:48:26 -05:00
Ross Thompson
38edbde966
Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
...
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
2022-09-23 11:46:53 -05:00
Ross Thompson
bcca9a62c5
Fixed up IFU ahb interface names and widths.
2022-09-19 10:54:22 -05:00
Ross Thompson
cb34b7c98f
Found the ahb burst bug.
...
We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests. It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads. The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads. In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes.
2022-09-17 20:30:01 -05:00
Ross Thompson
cea012a640
renamed multimanager to multicontroller.
2022-09-14 14:03:37 -05:00
Ross Thompson
2c86badeb2
pipelining of fetch into evict AHB requests.
2022-09-13 17:51:55 -05:00
Ross Thompson
0904951a8c
Oups the ahbinterface.sv was accidentally named abhinterface.sv.
2022-09-08 13:21:37 -05:00
Ross Thompson
bc15f6c5e4
Added logic to make burst optional.
2022-09-06 09:21:21 -05:00
Ross Thompson
20643ffc4a
Names changes.
2022-09-05 20:49:35 -05:00
Ross Thompson
2554f96662
Cleaned up hacks to ram.
2022-09-04 14:52:40 -05:00
Ross Thompson
221367efb9
Disabled AHB burst mode, which discovered a bug.
...
Multimanger bug in how back to back requests were arbitrated.
2022-09-03 22:31:41 -05:00
Ross Thompson
00cffb0aa5
Renamed state in buscachefsm to match AHB phases.
2022-09-02 17:17:40 -05:00
Ross Thompson
6f2acf678c
Renamed states in busfsm to match AHB phases and book names.
2022-09-02 17:12:36 -05:00
Ross Thompson
6f366c643d
Possible fix for AHB trailing ~HREADY bug.
2022-09-02 16:58:35 -05:00
Ross Thompson
eae56a890c
marked possible improvement to ahb bus fsms.
2022-08-31 23:57:08 -05:00
Ross Thompson
7598fbcb3b
Reduced busfsm to 3 states!
2022-08-31 16:11:59 -05:00
Ross Thompson
6f3dad8207
Simplified.
2022-08-31 15:40:56 -05:00
Ross Thompson
12d1ef2144
More renaming.
2022-08-31 14:49:08 -05:00
Ross Thompson
c03b202ab0
Moved files.
...
Encapsulated ahbinterface.
2022-08-31 14:45:01 -05:00
Ross Thompson
1b339f0547
Moved files around.
2022-08-31 14:08:06 -05:00
Ross Thompson
0d3f03ac06
Major cleanup of multimanager.
2022-08-31 12:40:25 -05:00
Ross Thompson
77cc549cfa
Cleanup multimanager.
2022-08-31 12:04:44 -05:00
Ross Thompson
eaa9cbda46
cleanup of multimanager.
2022-08-31 11:38:06 -05:00
Ross Thompson
315f662eb9
More progress.
2022-08-30 15:27:19 -05:00
Ross Thompson
8cf3c7b352
new cache bus fsm not working but lints.
...
Forgot a few files in the last commit.
2022-08-30 10:58:07 -05:00
Ross Thompson
233777f744
Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager.
2022-08-29 13:01:24 -05:00
David Harris
5340c45dfc
Separated busdp for cache from simpler logic for no cache
2022-08-25 17:54:04 -07:00
David Harris
9a92bfe095
Simplified swbytemask
2022-08-25 17:32:16 -07:00
David Harris
902d2067ba
Removed delayed AHB signals from top level
2022-08-25 15:34:14 -07:00
David Harris
302a7fa294
Extended HADDR to PA_BITS
2022-08-25 13:11:36 -07:00
David Harris
07225cabb7
Fixed brom name
2022-08-25 12:48:00 -07:00
David Harris
1226b2889e
ahblite cleanup
2022-08-25 12:44:25 -07:00
David Harris
3ba961d1a8
renamed BusBuffer to FetchBuffer
2022-08-25 10:44:39 -07:00
David Harris
dda3b441d7
Continued busdp/ebu simplification
2022-08-25 10:20:02 -07:00
David Harris
aba914ea5e
Renamed AHB signals coming out of LSU to LSH_<AHBNAME>
2022-08-25 09:52:08 -07:00
David Harris
c789b5789c
renamed GrantData to LSUGrant
2022-08-22 13:47:19 -07:00
Ross Thompson
57fcf0ef79
Fixed fstore2 in cache?
2022-08-01 22:04:44 -05:00
Ross Thompson
797d9e3610
Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris.
2022-08-01 21:12:25 -05:00
Ross Thompson
3612db2d70
pulled swbbytemask out of subword write.
2022-08-01 20:48:45 -05:00
David Harris
5ae88dbef0
Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc
2022-07-08 09:09:02 +00:00
David Harris
72e216d053
APB CLINT passing regression
2022-07-05 15:51:35 +00:00
