306 Commits

Author	SHA1	Message	Date
Ross Thompson	f89c1d91dc	Renamed most signals inside cache.sv so they are agnostic to i or d.	2022-01-04 23:52:42 -06:00
Ross Thompson	9eda7c12bd	the i and d caches now share common verilog.	2022-01-04 23:40:37 -06:00
Ross Thompson	b06c3b8acd	parameterized the caches with the goal of using common rtl for both i and d caches.	2022-01-04 22:40:51 -06:00
Ross Thompson	06168e67e4	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
David Harris	1f07470477	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 19:47:51 +00:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00