David Harris
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80666f0a71
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Added ASID & Global PTE handling to TLB CAM
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2021-07-04 17:52:00 -04:00 |
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David Harris
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9645b023c9
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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Ross Thompson
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7b3716c281
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-07-02 13:56:49 -05:00 |
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David Harris
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76a43eb468
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Optimized PMP checker logic and added support for configurable number of PMP registers
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2021-07-02 11:05:25 -04:00 |
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Kip Macsai-Goren
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d7e518991e
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Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.
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2021-06-24 20:01:11 -04:00 |
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bbracker
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23f479d225
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remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
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2021-06-20 22:38:25 -04:00 |
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David Harris
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35c74348a4
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allow all size memory access in CLINT; added underscore to peripheral address symbols
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2021-06-18 08:05:50 -04:00 |
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David Harris
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da8eb7749f
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Started simplifying PMA checker
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2021-06-17 16:28:06 -04:00 |
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David Harris
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0ffbd03139
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More verilator fixes, but bpred is broken
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2021-06-09 21:03:03 -04:00 |
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David Harris
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2952550db7
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More PMP entries
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2021-06-08 15:33:06 -04:00 |
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David Harris
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90e5781471
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Start to parameterize number of PMP Entries
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2021-06-08 15:29:22 -04:00 |
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Kip Macsai-Goren
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a95a7a7b82
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working version with new mmu comments, old boottim values
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2021-06-08 15:20:25 -04:00 |
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David Harris
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b613f46c2d
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Resized BOOT TIM to 1 KB
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2021-06-08 14:04:32 -04:00 |
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David Harris
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2ae5ca19b5
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Continued merge
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2021-06-07 12:49:47 -04:00 |
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David Harris
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ff62000e2c
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Second attept to commit refactoring config files
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2021-06-07 12:37:46 -04:00 |
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David Harris
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dc0b19dfaa
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Merge difficulties
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2021-06-07 09:50:23 -04:00 |
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David Harris
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d5ec797ba4
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Refactored configuration files and renamed testbench-busybear to testbench-linux
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2021-06-07 09:46:52 -04:00 |
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Kip Macsai-Goren
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22e8e06ac7
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moved privilege dfinitions into wally-constants, upgraded relevant includes
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2021-06-04 17:55:07 -04:00 |
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David Harris
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a26bf37be8
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Started MMU
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2021-06-04 11:59:14 -04:00 |
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David Harris
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0674f5506e
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moved shared constants to a shared directory
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2021-06-03 22:41:30 -04:00 |
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Kip Macsai-Goren
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40cfa86935
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Edited and added constants to support SV48
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2021-06-01 17:49:45 -04:00 |
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James E. Stine
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2eeb12c674
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Updates to muldiv.sv for 32-bit div/rem
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2021-06-01 15:31:07 -04:00 |
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Katherine Parry
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06af239e6c
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FMV.D.X imperas test passes
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2021-05-20 22:17:59 -04:00 |
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James E. Stine
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44dc665fc5
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Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA)
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2021-05-18 13:48:44 -05:00 |
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Katherine Parry
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9464c9022d
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floating point infinite loop removed from imperas tests
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2021-05-18 10:42:51 -04:00 |
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Shriya Nadgauda
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c5a306426a
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finishing merge conflict changes
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2021-05-03 22:15:05 -04:00 |
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Shriya Nadgauda
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b7159652f6
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merge conflict fixes
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2021-05-03 22:12:30 -04:00 |
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Shriya Nadgauda
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968994c04a
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updated pipeline tests
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2021-05-03 22:07:36 -04:00 |
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Ross Thompson
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818c0abc89
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Fixed memory size in configs for rv32ic and rv64ic.
Removed warning on call to $fscanf.
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2021-04-29 17:36:46 -05:00 |
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Ross Thompson
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72363f5c66
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Added the ability to exclude branch predictor.
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2021-04-26 14:27:42 -05:00 |
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bbracker
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74b35ac57a
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greatly improved PLIC register interface
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2021-04-22 11:22:01 -04:00 |
|
Noah Boorstin
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6954e6df4c
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buildroot: sim is now running!
yes it only gets through 5 instructions right now. Yes that's my fault.
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2021-04-17 14:44:32 -04:00 |
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bbracker
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290b3424e5
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-04-15 21:09:27 -04:00 |
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bbracker
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368c94d4ff
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working GPIO interrupt demo
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2021-04-15 21:09:15 -04:00 |
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Domenico Ottolia
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92bb38fa8c
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Add support for vectored interrupts
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2021-04-15 19:13:42 -04:00 |
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Shreya Sanghai
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0369fc5d1e
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Cherry Pick merge of Shreya's localhistory predictor changes into main.
fixed minor bugs in localHistory
|
2021-04-15 09:04:36 -05:00 |
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Thomas Fleming
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303c2c4839
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Implement support for superpages
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2021-04-08 02:44:59 -04:00 |
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bbracker
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31c6b2d01f
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Yee hoo first draft of PLIC plus self-checking tests
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2021-04-04 06:40:53 -04:00 |
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Thomas Fleming
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7126ab7864
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Complete basic page table walker
|
2021-03-30 22:19:27 -04:00 |
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bbracker
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11d4a8ab34
|
first pass at PLIC interface
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2021-03-22 10:14:21 -04:00 |
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Shreya Sanghai
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bbe0957df5
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Merge branch 'gshare' into main
Conflicts:
wally-pipelined/regression/wave.do
|
2021-03-18 17:25:48 -04:00 |
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Ross Thompson
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1091dd10c1
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Switched to gshare from global history.
Fixed a few minor bugs.
|
2021-03-18 16:05:59 -05:00 |
|
Noah Boorstin
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bc1a0c6ee7
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change ifndef to generate/if
|
2021-03-18 12:50:19 -04:00 |
|
Noah Boorstin
|
a2b0af460e
|
everyone gets a bootram
|
2021-03-18 12:35:37 -04:00 |
|
Shreya Sanghai
|
36f0631203
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added gshare and global history predictor
|
2021-03-16 17:03:01 -04:00 |
|
Shreya Sanghai
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9eed875886
|
added global history branch predictor
|
2021-03-16 16:06:40 -04:00 |
|
Shreya Sanghai
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74f1641c5a
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Merge branch 'counters' into main
added a configurable number of performance counters
|
2021-03-16 11:01:30 -04:00 |
|
Ross Thompson
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4c8952de6a
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Converted branch predictor preloads to use system verilog rather than modelsim's load command.
|
2021-03-15 12:39:44 -05:00 |
|
Thomas Fleming
|
1294235837
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
|
2021-03-11 00:15:58 -05:00 |
|
David Harris
|
17c0f9629a
|
WALLY-LRSC atomic test passing
|
2021-03-09 09:28:25 -05:00 |
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