Rose Thompson
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e6902eb4d2
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Ok. How does it still work? testbench-imperas.sv the same as testbench.sv now.
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2024-05-17 16:08:14 -05:00 |
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Rose Thompson
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d9807bb909
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This is crazy. I'm merging testbench.sv into testbench-imperas.sv to find the point when it stops working. But each logical point where it would stop working it keeps working. For example moving readmemh from initial to always block.
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2024-05-17 14:45:37 -05:00 |
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Rose Thompson
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a885240fbd
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temporary commit to help debug merging testbench.sv with testbench-imperas.sv
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2024-05-17 12:36:00 -05:00 |
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David Harris
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160c11d786
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Integrating riscv-dv coverage
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2024-04-24 10:17:49 -07:00 |
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Quswar Abid
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1b18568d87
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the fix Rose provided in meeting
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2024-04-17 09:39:21 -07:00 |
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David Harris
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b386331cc8
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Changed '0 to 0 where possible per Chapter 4 style guidelines
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2024-03-06 05:48:17 -08:00 |
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David Harris
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b3ff1035c4
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Propagated MIP-based tracer interrupts to testbench-linux-imperas
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2023-12-21 11:47:49 -08:00 |
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David Harris
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45b5658d06
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Updated Imperas testbench to use MIP bits to communicate pending interrupts
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2023-12-21 11:05:26 -08:00 |
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David Harris
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b268a3b9d3
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Added SPI support to Imperas testbenches
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2023-12-07 09:44:31 -08:00 |
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David Harris
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cfaeeae25a
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Added cmoz support to imperas.ic and adjusted imperas testbench to no longer need FPGA parameter
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2023-11-15 08:15:01 -08:00 |
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David Harris
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b0dbf3a984
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Testbench fixes to add SPI and make string pp static in testbench.fp to solve compiler issue
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2023-11-04 20:36:05 -07:00 |
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David Harris
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dd072c80f2
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Updated testbenches to capture InstrM because it may be optimized out of IFU
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2023-11-03 05:24:15 -07:00 |
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Rose Thompson
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8f2ca2ae15
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Added missing files.
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2023-10-13 15:10:58 -05:00 |
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