6 Commits

Author	SHA1	Message	Date
Ross Thompson	d98baf90a3	Replaced async reset flip flops with sync reset flip flops in cache and bpread.	2021-10-27 09:57:11 -05:00
Ross Thompson	f1107c5d7b	Corrected a number of bugs in the branch predictor. ... Added performance counters to individually track branches; jumps, jump register, jal, and jalr; return. jump and jump register are special cases of jal and jalr. Similarlly return is a special case of jalr. Also added counters to track if the branch direction was wrong, btb target wrong, or the ras target was wrong. Finally added one more counter to track if the BP incorrectly predicts a non-cfi instruction.	2021-03-31 11:54:02 -05:00
Ross Thompson	ace39940b4	Fixed RAS errors. Still some room for improvement with the BTB and RAS.	2021-03-23 23:00:44 -05:00
Ross Thompson	72d25d4443	Fixed a bunch of bugs with the RAS.	2021-03-23 21:49:16 -05:00
Ross Thompson	c856003f73	RAS needs to be reset or preloaded. For now I just reset it. ... Fixed bug with the instruction class. Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version.	2021-02-19 20:09:07 -06:00
Ross Thompson	ca546beaf8	We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS. ... This is not yet tested but the system verilog does compile.	2021-02-15 14:51:39 -06:00