Ross Thompson
c91530aa17
Updates to wave file.
2023-06-14 10:49:09 -05:00
Ross Thompson
d9f7daf5e0
The new testbench is almost working except the shadow copy is not working.
2023-06-12 15:08:23 -05:00
Ross Thompson
bbe3f1caf0
Created temporary wrapper for lint.
2023-06-12 11:49:51 -05:00
David Harris
df212ce7d8
Merge pull request #312 from ross144/main
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Fixed typo in coremark makefile.
2023-06-06 05:44:22 -07:00
Ross Thompson
7cd727c918
Oups forgot to include updates to the lint script itself.
2023-05-31 11:00:38 -05:00
David Harris
97763beb75
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-05-30 13:53:28 -07:00
Ross Thompson
0f8049a04f
Hacked it together, but I think testfloat is working.
2023-05-30 15:51:13 -05:00
David Harris
0c718f2b71
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-05-30 13:40:56 -07:00
Ross Thompson
e859609a6e
Updated do files for parameterization.
2023-05-30 15:38:03 -05:00
David Harris
bbe0f0c093
Exclusions for decoders with new parameterization
2023-05-30 01:04:39 -07:00
David Harris
ebdf676eec
Eliminated merging non-existent coverage
2023-05-30 00:38:30 -07:00
Ross Thompson
903f2f9063
Merge branch 'param-lim-merge'
2023-05-26 16:25:35 -05:00
Ross Thompson
d3123fc00a
Updated a large number of the source files to use parameters rather than `defines. Based on Lim's work. So far there is no simulation slow down.
2023-05-24 14:05:44 -05:00
Ross Thompson
6509463f3d
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-05-24 13:00:50 -05:00
Ross Thompson
c5aeb08e5c
Trying to figure out why the parameterization slowed down modelsim so much.
2023-05-24 12:44:42 -05:00
David Harris
ee3660b0f2
Removed unnecessary imperas tests from coverage
2023-05-23 15:43:11 -07:00
David Harris
c223c18f34
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-05-22 11:27:57 -07:00
David Harris
6e8a313930
Verilate start
2023-05-22 10:30:39 -07:00
Ross Thompson
1dc7fb567b
Merge branch 'localhistory'
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Repair to wave file.
Created implementations of local history. Part of my Ph.D. research.
2023-05-22 10:13:31 -05:00
Ross Thompson
c68dae0b0e
Repaired wave file.
2023-05-22 10:09:33 -05:00
Ross Thompson
cae4448808
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-05-22 10:06:42 -05:00
Ross Thompson
d57a33fb6b
Repaired wave file.
2023-05-22 09:50:34 -05:00
David Harris
d086dbffb4
Factored FMA tests out of the main 32/64 f/d tests to run in parallel and speed up sim
2023-05-16 11:37:01 -07:00
Ross Thompson
03823a9bc1
Partially working local history repair.
2023-05-11 14:56:26 -05:00
Ross Thompson
35a59a1193
I think ahead pipelining is working for local history.
2023-05-03 12:52:32 -05:00
David Harris
34880771af
Fixed IROM coverage issues in IFU
2023-05-01 08:32:52 -07:00
David Harris
c1786bfec8
IMMU exclude non word-sized accesses
2023-05-01 08:14:19 -07:00
David Harris
d5c350c597
Merged coverage exclusions for PMP
2023-04-28 08:04:25 -07:00
David Harris
ca5a71bbe5
PMA Checker coverage
2023-04-28 07:53:59 -07:00
Liam
6803347a49
Pmpadrdecs test cases changing AdrMode to 2 or 3
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Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3
Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv
2023-04-27 12:23:35 -07:00
David Harris
e43de9c194
Merge pull request #282 from ross144/main
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Arty A7 board support, ImperasDV linux boot, CVW_v0.9 tag
2023-04-27 07:23:10 -07:00
David Harris
0ad5165795
Merge pull request #283 from SydRiley/main
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Resolving unpackinput coverage issue with BadNaNBox, and increasing ifu and lsu coverage% through exclusions
2023-04-26 15:40:01 -07:00
Sydeny
a40cc17dc7
For ifu and lsu exclusions added missing row numbers
2023-04-26 15:30:22 -07:00
Ross Thompson
e72fa0c081
Modified the imperas linux scripts so they run without reporting hundreds of gigabytes of data.
2023-04-26 17:29:57 -05:00
Sydeny
efcb59ee35
Exclusion in the ifu and lsu to increase coverage, added missing row numbers
2023-04-26 15:26:39 -07:00
Sydeny
25b69a47a1
Excluding untoggled signals in ifu and lsu, ifu coverage from 83.68% to 84.06% and lsu from 93.45% to 93.58%
2023-04-26 14:37:55 -07:00
Sydeny
069ca0ec29
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-04-26 03:00:25 -07:00
Sydeny
f5258d3b22
added comments to exclusions
2023-04-26 03:00:13 -07:00
Alec Vercruysse
6299c0ef0b
Cacheway Exclude FlushStage=1 when SetValidWay=1
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We determined that this case is not hit even for i$, so this
case is also excluded separately for i$. It could be a better
idea to remove the ~FlushStage check completely (if we're sure).
My reasoning for this one is written as a comment in the exclusion
script: since a pipeline stall is asserted by the cache in the fetch
stage (which happens before going into the WRITE_LINE state and
asserting SetValidWay), there seems to be no way to trigger
a FlushStage (FlushW for D$) while the stallM is active.
2023-04-25 20:30:46 -07:00
Alec Vercruysse
9f417ee93d
extend invalidatecache d$ exclusion to statement coverage
2023-04-25 17:00:13 -07:00
Diego Herrera Vicioso
c681789296
Excluded coverage for impossible cases in wficountreg and status.MPRV
2023-04-24 02:06:53 -07:00
David Harris
8be5ed9b67
Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage.
2023-04-22 12:22:45 -07:00
Ross Thompson
ffa686a605
Merge pull request #264 from davidharrishmc/dev
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Added -fp flag to run arch64d/f tests in coverage
2023-04-20 09:26:16 -05:00
David Harris
24e60c232d
Merge pull request #262 from SydRiley/main
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removed comments for fixed bugs in fpu, increased coverage in fpu, ifu, and lsu: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%
2023-04-19 14:49:50 -07:00
Sydeny
039a06ec95
clarifying comments in exclusions
2023-04-19 14:47:34 -07:00
Sydeny
b76ed145e6
removed comments for fixed bugs in fpu, increased coverage: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%
2023-04-19 13:30:12 -07:00
David Harris
a3f3967f59
Added -fp flag to run arch64d/f tests in coverage
2023-04-19 13:07:07 -07:00
Alec Vercruysse
b52512b1ae
D$ scope-specific coverage exclusions (I$ logic that never fires)
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The InvalidateCache signal in the D$ is for I$ only, which
causes some coverage issues that need exclusion.
Another manual exclusion is due to the fact that D$ writeback, flush,
write_line, or flush_writeback states can't be cancelled by a flush,
so those transistions are excluded.
There is some other small stuff to review (logic simplification,
or an exclusion pragma if removing the redundent logic would
make it harder to understand the code, as is the case in the
FlushAdrCntEn assign statement, in my opinion).
2023-04-19 01:34:01 -07:00
Alec Vercruysse
e3593800d9
fix unhit exclusion in fdivsqrtfsm
2023-04-19 01:34:01 -07:00
Sydeny
f0ff1a4447
increasing lsu coverage by excluding the pmachecher/adrdecs/clintdec or uncoreram signal SizeValid becauseany size is valid so signal is always 1
2023-04-17 14:19:48 -07:00
