11 Commits

Author	SHA1	Message	Date
David Harris	b09fd0d0a8	Simplified tlbmixer mux to and-or	2021-07-08 23:34:24 -04:00
David Harris	4d53a935b3	Fixed missing stall in InstrRet counter	2021-07-08 20:08:04 -04:00
David Harris	b1592a0542	TLB cleanup to match diagrams	2021-07-08 16:52:06 -04:00
Abe	244e197348	Changed SvMode to SVMode on line 76	2021-07-06 23:28:58 -04:00
Kip Macsai-Goren	1652e09b38	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-06 18:54:41 -04:00
David Harris	2b26bbbbd7	more TLB name touchups	2021-07-06 18:39:30 -04:00
Kip Macsai-Goren	8dfa28125f	fixed upper bits page fault signal	2021-07-06 18:32:47 -04:00
David Harris	73024fee2d	connected signals in tlb by name instead of .*	2021-07-06 17:22:10 -04:00
David Harris	78850bfcd8	MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB	2021-07-06 15:29:42 -04:00
David Harris	087bed3b67	Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines	2021-07-06 10:38:30 -04:00
David Harris	69c0358ffd	Created tlbcontrol module to hide details	2021-07-06 03:25:11 -04:00