1199 Commits

Author	SHA1	Message	Date
David Harris	e2600bc55d	cleaning up FSM	2021-07-17 04:26:41 -04:00
David Harris	52a7dd9ac0	Simplify FSM	2021-07-17 04:12:31 -04:00
David Harris	31a3b39e5c	Pulled TranslationPAdr mux out of HPTW FSM	2021-07-17 04:06:26 -04:00
David Harris	7eb03c2ff6	Simplified bad PTE detection	2021-07-17 03:30:17 -04:00
David Harris	b8ee8a8ce0	Pulled out shared PTEReg	2021-07-17 03:21:09 -04:00
David Harris	d3974fafdd	Flip-flop clean-up	2021-07-17 03:15:47 -04:00
David Harris	de72dff382	Flip-flop clean-up	2021-07-17 03:12:24 -04:00
David Harris	a5ac606dda	Flip-flop clean-up	2021-07-17 03:10:17 -04:00
David Harris	2b0f8e9cf6	Started pagetablewalker cleanup: combined state flops shared for both RV versions	2021-07-17 02:53:52 -04:00
David Harris	fe8910437a	Replaced separate PageTypeF and PageTypeM with common PageType	2021-07-17 02:31:23 -04:00
David Harris	622a14cbdd	Removed more unused signals from ahblite	2021-07-17 02:21:54 -04:00
David Harris	52fcc47cdf	Removed rest of HRDATAW from ahblite	2021-07-17 02:15:24 -04:00
David Harris	1d171d7ea6	Commented out HRDATAW logic in ebu	2021-07-17 02:10:57 -04:00
David Harris	d6f859da18	renamed or_rows.sv	2021-07-16 20:17:03 -04:00
David Harris	f69393f197	Reduced size of physical memory by 16 for performance	2021-07-16 20:10:12 -04:00
Kip Macsai-Goren	3d14d573a0	included virtual memory tests in testbench	2021-07-16 17:57:24 -04:00
Ross Thompson	e9649eb1f5	Made furture progress in the mmu tests.	2021-07-16 15:56:06 -05:00
Ross Thompson	965f34d78f	Added guide for Ben to do linux conversion.	2021-07-16 15:04:30 -05:00
Ross Thompson	abce241f68	Also changed the shadow ram's dcache copy widths. ... Merge branch 'dcache' into main	2021-07-16 14:21:09 -05:00
Ross Thompson	6ab7cd0f4d	Updated the config so the tim has a bigger range.	2021-07-16 12:35:00 -05:00
Ross Thompson	bebc7cc5e3	Updated wave file.	2021-07-16 12:34:37 -05:00
Ross Thompson	d3715acf2d	Fixed walker fault interaction with dcache.	2021-07-16 12:22:13 -05:00
bbracker	e51ab63a86	reduce number of UART ports to 1	2021-07-16 12:42:29 -04:00
bbracker	d38109bc1c	changed stop of linux boot from arch_cpu_idle to do_idle	2021-07-16 12:27:15 -04:00
Ross Thompson	5ca7dc619c	Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues.	2021-07-16 11:12:57 -05:00
bbracker	f7092c60d1	incremental linux config de-bloating	2021-07-16 12:08:58 -04:00
bbracker	629d48f20f	incremental linux config de-bloating	2021-07-16 11:33:11 -04:00
bbracker	0f1060ceb7	incremental linux config de-bloating	2021-07-16 11:15:25 -04:00
bbracker	fcb63a409a	incremental linux config de-bloating	2021-07-16 01:58:21 -04:00
bbracker	0a1aa821b8	incremental linux config de-bloating	2021-07-16 01:54:36 -04:00
bbracker	149be959e0	incremental linux config de-bloating	2021-07-16 01:43:16 -04:00
bbracker	e5e3a60574	incremental linux config de-bloating	2021-07-16 01:33:51 -04:00
bbracker	7266b29656	incremental linux config de-bloating	2021-07-16 01:25:41 -04:00
bbracker	09de4ded87	incremental linux config de-bloating	2021-07-16 01:00:12 -04:00
bbracker	f7b43211ac	incremental linux config de-bloating	2021-07-16 00:46:22 -04:00
bbracker	c5e9734851	incremental linux config de-bloating	2021-07-16 00:41:18 -04:00
bbracker	d6a4b8ccfa	incremental linux config de-bloating	2021-07-16 00:34:41 -04:00
bbracker	285e5941e2	incremental linux config de-bloating	2021-07-16 00:16:12 -04:00
bbracker	a6071f3fb0	incremental linux config de-bloating	2021-07-16 00:10:31 -04:00
bbracker	226474051d	incremental linux config de-bloating	2021-07-15 23:53:15 -04:00
bbracker	0a15468fd5	incremental linux config de-bloating	2021-07-15 23:30:24 -04:00
bbracker	588a7d0341	incremental linux config de-bloating	2021-07-15 23:12:21 -04:00
bbracker	703b72fb89	incremental linux config de-bloating	2021-07-15 23:00:20 -04:00
bbracker	847edccbd7	incremental linux config de-bloating	2021-07-15 21:33:52 -04:00
bbracker	2091a7104e	incremental linux config de-bloating	2021-07-15 20:54:36 -04:00
bbracker	a4f9d7a6e5	working linux config	2021-07-15 18:49:54 -04:00
Kip Macsai-Goren	ba5bb12e26	Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction.	2021-07-15 18:30:29 -04:00
bbracker	58cbce940a	stripped down busybox a bit	2021-07-15 16:07:56 -04:00
Ross Thompson	96aa106852	Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.	2021-07-15 11:56:35 -05:00
Ross Thompson	4549a9f1c9	Merge branch 'main' into dcache	2021-07-15 11:55:20 -05:00