63 Commits

Author	SHA1	Message	Date
bbracker	5327dcfcc8	instrfaults not respecting stalls bugfix	2021-03-25 00:16:26 -04:00
Ross Thompson	cdb7d15709	Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.	2021-03-24 15:56:55 -05:00
Shreya Sanghai	09b90557f7	PC counts branch instructions	2021-03-23 14:25:51 -04:00
Shreya Sanghai	dfc86539cc	Merge branch 'gshare' into main ... Conflicts: wally-pipelined/regression/wave.do	2021-03-18 17:25:48 -04:00
Thomas Fleming	062c4d40da	Connect tlb, pagetablewalker, and memory	2021-03-18 14:35:46 -04:00
Shreya Sanghai	23a7c8cd92	made performance counters count branch misprediction	2021-03-16 11:24:17 -04:00
Thomas Fleming	e48dc38869	Export SATP_REGW from csrs to MMU modules	2021-03-05 01:22:53 -05:00
David Harris	73920282af	Eliminated flushing pipeline on CSR reads	2021-02-26 17:00:07 -05:00
David Harris	cc42655789	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
David Harris	429f48e766	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	bb83fda1d8	Moved writeback pipeline registers from datapth into DMEM and CSR	2021-02-02 13:02:31 -05:00
David Harris	92bf1674b4	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	07af481b67	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00