7 Commits

Author	SHA1	Message	Date
Ross Thompson	e141a00934	Cleaned up the linux testbench by removing old code and signals. ... Added back in the csr checking logic. Added code to force timer, external, and software interrupts by using the expected values from qemu's (m/s)cause registers. Still need to prevent wally's timer interrupt.	2021-08-13 14:39:05 -05:00
Ross Thompson	cce0571925	Fixed another bug with the atomic instrucitons implemention in the dcache.	2021-08-08 22:50:31 -05:00
Ross Thompson	d3be04b7de	Fixed another bug with AMO. If the CPU stalled as an AMO was finishing, the write to the ... cache's SRAM would occur. Then in the next cycle the SRAM would be reread while stalled providing the new update dated rather than the correct older value.	2021-08-08 11:42:10 -05:00
Ross Thompson	fc7016eea6	Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic. ... Fixed logic for trace update in the M and W stages. The M stage should not update if there is an instruction fault.	2021-08-08 00:28:18 -05:00
Ross Thompson	0bfbcef8ab	Now past the CLINT issues.	2021-08-06 16:16:39 -05:00
Ross Thompson	9be10cdc8b	Partial conversion of the linux trace checking to read in the file in the Memory Stage so it is possible to overwrite registers, memory, and interrupts.	2021-08-06 16:06:50 -05:00
Ross Thompson	c749d08542	fixed the read timer issue but we still have problems with interrupts and i/o devices.	2021-08-06 10:16:06 -05:00