David Harris
e03912f64c
Cleaned up name of MTIME register in CSRC
2021-06-18 07:53:49 -04:00
bbracker
7d1469a06c
provide time and timeh CSRs based on CLINT's counter
2021-06-17 08:38:30 -04:00
bbracker
7a652139b5
mcause test fixes and s-mode interrupt bugfix
2021-06-16 17:37:08 -04:00
David Harris
79ee817d91
Reverted MIDELEG and MEDELEG to XLEN so busybear passes
2021-06-10 23:47:32 -04:00
David Harris
9dd3857c26
Fixed lint WIDTH errors
2021-06-09 20:58:20 -04:00
David Harris
9a17556de4
Start to parameterize number of PMP Entries
2021-06-08 15:29:22 -04:00
bbracker
28abd28b1f
fixed InstrValid signals and implemented less costly MEPC loading
2021-06-02 10:03:19 -04:00
bbracker
a45b61ede9
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-28 23:11:37 -04:00
Thomas Fleming
86a93d77b4
Implement PMP checker and revise PMA checker
2021-05-03 17:37:42 -04:00
Thomas Fleming
10c7260980
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-29 16:30:00 -04:00
ushakya22
de23edcfb9
fix to pcm bug
2021-04-29 15:21:08 -04:00
Thomas Fleming
e091f430e0
Clean up PMA checker and begin PMP checker
2021-04-29 02:20:39 -04:00
Ross Thompson
9e40fb072c
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
Thomas Fleming
70c801331a
Implement virtual memory protection
2021-04-21 19:58:36 -04:00
Domenico Ottolia
e02ff60b07
Fix synthesis warnings for privileged unit (replace 'initial' settings)
2021-04-20 17:57:56 -04:00
Domenico Ottolia
1bdfac6a77
Cause an Illegal Instruction Exception when attempting to write readonly CSRs
2021-04-08 05:12:54 -04:00
Ross Thompson
f1107c5d7b
Corrected a number of bugs in the branch predictor.
...
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
2021-03-31 11:54:02 -05:00
Thomas Fleming
4b2765f8e2
Complete basic page table walker
2021-03-30 22:19:27 -04:00
Ross Thompson
cdb7d15709
Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.
2021-03-24 15:56:55 -05:00
Shreya Sanghai
09b90557f7
PC counts branch instructions
2021-03-23 14:25:51 -04:00
Shreya Sanghai
23a7c8cd92
made performance counters count branch misprediction
2021-03-16 11:24:17 -04:00
Thomas Fleming
e48dc38869
Export SATP_REGW from csrs to MMU modules
2021-03-05 01:22:53 -05:00
David Harris
73920282af
Eliminated flushing pipeline on CSR reads
2021-02-26 17:00:07 -05:00
David Harris
7737b0f709
Fixed fetch stall after jump in bus unit
2021-02-23 09:08:57 -05:00
David Harris
cc42655789
More memory interface, ALU testgen
2021-02-15 10:10:50 -05:00
David Harris
bb83fda1d8
Moved writeback pipeline registers from datapth into DMEM and CSR
2021-02-02 13:02:31 -05:00
David Harris
92bf1674b4
Moved fpu to temporary location to fix compile and cleaned up interface formatting
2021-02-01 23:44:41 -05:00
David Harris
07af481b67
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
