Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
3,890 Commits 5 Branches 2 Tags 53 MiB
df411497e0
Commit Graph

224 Commits

Author SHA1 Message Date
Kip Macsai-Goren
69e79ccdf3 Allowed commenting in signature files 2022-02-06 02:05:59 +00:00
David Harris
0feb624bab Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration 2022-02-06 01:22:40 +00:00
bbracker
186267e35a Remove rv32e tests from rv32i_m Makefrag so that make XLEN=32 works 2022-02-05 21:34:50 +00:00
David Harris
16b5fee795 RV32e tests 2022-02-04 14:30:36 +00:00
David Harris
3cc20bdd0d Added E tests to repo 2022-02-03 23:42:31 +00:00
David Harris
e490705865 E tests 2022-02-03 22:55:55 +00:00
David Harris
761dae72fe Config file & wally-riscv-arch-test cleanup 2022-02-02 16:35:52 +00:00
Ross Thompson
a9b4f9b1e7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-01 10:50:38 -06:00
Ross Thompson
99bb281944 Updated fpga's bootloader to reflect the changes to the gpio address change. 2022-02-01 10:43:24 -06:00
Kip Macsai-Goren
97f5878ec4 Renamed test library 2022-01-31 20:11:21 +00:00
Kip Macsai-Goren
4d8ca0d031 updated minfo test to account for no mconfigptr 2022-01-31 20:11:21 +00:00
Kip Macsai-Goren
63f4baf357 fixed CSR read-only test to have correct output 2022-01-31 20:11:21 +00:00
Kip Macsai-Goren
1077cf08b0 added machine info test that uses new test library 2022-01-31 05:54:43 +00:00
Kip Macsai-Goren
5386f1b4fa tentatively remade test lib to use macros for more flexibility 2022-01-31 05:54:43 +00:00
Kip Macsai-Goren
01d6c3a4b9 converted library to header file for RISCV test compliance 2022-01-31 05:54:43 +00:00
Kip Macsai-Goren
e3ea593ed8 updated tests to use test title instead of number encoding 2022-01-31 05:54:42 +00:00
David Harris
975c0e72c8 Set up rv32emc config 2022-01-27 14:37:58 +00:00
Ross Thompson
aa474ad588 Added generated source code for the wally riscv arch tests rv32i_m and rv64i_m. 2022-01-27 08:11:46 -06:00
David Harris
0023c4cb57 Adjusted test cases for new GPIO base address 2022-01-26 19:15:48 +00:00
David Harris
c60bb68bff Testgen working for Lab 2 2022-01-26 18:01:51 +00:00
David Harris
f90e58ff34 New testgen.py 2022-01-26 17:21:02 +00:00
kaveh Pezeshki
3314fb48c4 added qemu patches in tests/linux-testgen/qemu 2022-01-24 07:52:07 +00:00
David Harris
380e990def moved fp to tests 2022-01-14 23:05:59 +00:00
David Harris
36d49a8a74 Moved fp tests from testbench to tests/fp 2022-01-14 23:00:46 +00:00
Kip Macsai-Goren
c99456d5e7 Fixed PMA regions, Added passing PMA tests to regression 2022-01-10 22:08:26 +00:00
Kip Macsai-Goren
53f3a6dbab comment cleanup 2022-01-09 18:16:42 +00:00
Kip Macsai-Goren
9412a5ff2d updated PMA tests, everything passes except successful writes to protected regions. 2022-01-09 18:16:00 +00:00
Kip Macsai-Goren
a22dc4d163 changed test case types to lookup table instead of beq's 2022-01-09 16:56:37 +00:00
David Harris
eff9cec415 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-06 18:10:32 +00:00
David Harris
aca26de498 FPU debug and configurable logic cleanup 2022-01-06 18:10:25 +00:00
Kip Macsai-Goren
c949764a44 fixed 32 vs 64 bit copying error 2022-01-05 23:14:12 +00:00
Kip Macsai-Goren
bd977efc7b updated pma tests for simpler test lib 2022-01-05 22:10:12 +00:00
Kip Macsai-Goren
8a8f903342 updated tests to make correctly with output verification 2022-01-05 21:43:15 +00:00
Kip Macsai-Goren
706c95a383 allowed option for tests to make without spike simulation. added postverify back in for outputs 2022-01-05 21:17:54 +00:00
Kip Macsai-Goren
1db58744b0 updated pma tests to match simpler test library. They don't pass regression yet 2022-01-05 21:13:40 +00:00
Kip Macsai-Goren
46b0cb810d fixed arch tests to pass make, added 32 bit tests, addded all make-passing tests to tests.vh. 2022-01-04 21:30:38 +00:00
David Harris
115287adc8 Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
David Harris
77c00e996b Started adding asynchronous TIMECLK for CLINT 2022-01-02 21:18:16 +00:00
David Harris
e084c8868f Added wally-riscv-arch-test MMU tests and removed imperas MMU tests from regresssion 2021-12-30 17:22:18 +00:00
David Harris
da402f93cc Fixed page table entreis so WALLY-MMU-SV32, SV39, SV48 now run 2021-12-30 16:46:19 +00:00
David Harris
c3bfa53db0 Added partially working MMU tests 2021-12-29 03:14:16 +00:00
David Harris
69243f41ad Fixed imperas C tests 2021-12-26 04:45:06 +00:00
Ross Thompson
db76878581 Moved convert2bin.py to the tests directory. This file converts the qemu ram.txt output into a binary for copy to flash card. 
mv qemu patches to tests directory.
 2021-12-19 20:11:32 -06:00
Ross Thompson
8e4eacc18e Merge branch 'main' into fpga 2021-11-29 10:10:37 -06:00
Ross Thompson
e43aa6ead4 Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
bbracker
de8e2008d2 fix parseState.py to correctly take in PMPCFG 2021-11-24 16:52:51 -08:00
bbracker
13b65fa785 increase niceness of automatic checkpoint generation 2021-11-20 12:48:23 -08:00
David Harris
d243f4bcd1 Cleaning up CoreMark benchmark 2021-11-18 20:12:52 -08:00
David Harris
54fef3e2ca vert "Simplifying riscv-coremark" 
This reverts commit bdc212cf88.
 2021-11-18 18:40:13 -08:00
David Harris
bdc212cf88 Simplifying riscv-coremark 2021-11-18 17:15:40 -08:00
David Harris
b996598b37 CoreMark testing 2021-11-18 16:14:25 -08:00
David Harris
5a521e28ee Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-16 12:30:55 -08:00
bbracker
23bd24323b get current privilege level from GDB for checkpoints 2021-11-15 14:49:00 -08:00
David Harris
f96152fa31 bringing Coremark back to life 2021-11-10 12:43:31 -08:00
bbracker
24c5796680 genCheckpoint path bugfix 2021-11-06 15:25:10 -07:00
bbracker
e585a173e5 automated checkpoint generator 2021-11-06 14:37:49 -07:00
bbracker
d0ad8d3ae3 update tvLinker to new shared dir 2021-11-06 14:15:16 -07:00
bbracker
31d38286da make genCheckpoint accept instr count as argument 2021-11-06 14:14:15 -07:00
bbracker
1d3d7cbe1e fix merge conflict 2021-11-05 23:42:15 -07:00
bbracker
3077769cbd checkpoints now use binary ram files 2021-11-05 22:37:05 -07:00
bbracker
730c52da23 genCheckpoint syntax fix 2021-11-01 15:31:38 -07:00
bbracker
8563c0f016 linux testgen refactor 2021-11-01 14:09:49 -07:00
David Harris
db268471b6 added some missing files 2021-11-01 13:36:07 -07:00
David Harris
0c829dd62c simplified header and footer 2021-11-01 13:24:18 -07:00
David Harris
910957704b Add3d wally32i test 2021-11-01 13:17:49 -07:00
David Harris
4b57af9cff PIPELINE test running 2021-11-01 12:44:35 -07:00
David Harris
c306884e2c Adding custom Wally test infrastructure 2021-11-01 08:48:46 -07:00
David Harris
717f9d48e9 tesgen cleanup, added riscv-arch-test D tests 2021-10-29 22:31:48 -07:00
David Harris
f7acd31bcb rearranging testgen 2021-10-29 22:28:37 -07:00
David Harris
ca700610f8 removed referenc outputs 2021-10-26 08:51:49 -07:00
Ross Thompson
2f4ee26b60 Fixed issue with dtim (fpga) external abhlite select not triggering. 
Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
 2021-10-25 14:51:54 -05:00
David Harris
7732d38c36 lint cleaning and moved files into subdirectories 2021-10-23 08:53:32 -07:00
Ross Thompson
09dc3e1143 Merge branch 'main' into fpga 2021-10-20 16:24:55 -05:00
David Harris
0e4f6392d6 Move tests into subdirectory and moved wavedrom out of project 2021-10-20 09:03:21 -07:00