Ross Thompson
07308e2c14
Removed mark_debug from all source code.
2023-01-20 18:47:36 -06:00
Ross Thompson
b8a699270e
More cleanup and formatting.
2023-01-20 12:34:40 -06:00
Ross Thompson
4a2d02ab28
Formatting.
2023-01-20 11:51:10 -06:00
Ross Thompson
63577cbf4a
Cleanup dtim and irom.
2023-01-18 18:44:30 -06:00
Ross Thompson
b223e22642
Formatting.
2023-01-18 18:05:11 -06:00
Ross Thompson
c5c4a3c011
Formatting
2023-01-18 16:58:03 -06:00
Ross Thompson
32589a5efc
Formating.
2023-01-18 16:47:40 -06:00
Ross Thompson
c3096eea2a
Cleaned up ahbcacheinterface.
2023-01-17 22:13:56 -06:00
Ross Thompson
4720b28272
Formatting progress.
2023-01-17 22:10:31 -06:00
Ross Thompson
d21eef40d7
Added comments to dtim and ahbcacheinterface.
2023-01-17 21:56:55 -06:00
David Harris
dc74bcff5b
Clean up tabs
2023-01-15 18:23:09 -08:00
Ross Thompson
3a41854f2b
Completed review of LSU.
2023-01-11 19:06:03 -06:00
Ross Thompson
2f3bf9eaf5
Improved LSU formating.
2023-01-11 18:52:46 -06:00
Ross Thompson
a42d436962
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2023-01-11 17:15:49 -06:00
David Harris
7d93659f6b
changed name to CORE-V-WALLY
2023-01-11 15:15:08 -08:00
Ross Thompson
a024dbccd6
Updated header for LSU.
2023-01-11 17:15:07 -06:00
David Harris
b911056e66
Changed Wally to CORE-V Wally
2023-01-11 14:03:44 -08:00
David Harris
e92cffbb5e
Changed MIT license to Solderpad License
2023-01-10 11:35:20 -08:00
David Harris
9bdf79bfe6
Removed unused signals; added check for atomic in pmachecker
2023-01-07 05:59:56 -08:00
Ross Thompson
b5a85b55f1
Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
...
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
2022-12-23 15:10:37 -06:00
Ross Thompson
6b105bd217
Renamed IFU and LSU stalls.
2022-12-22 21:56:33 -06:00
Ross Thompson
9b9e954cc5
Cleanup comments.
2022-12-16 17:08:35 -06:00
Ross Thompson
5b38b4e639
Renamed CPUBusy in LSU.
2022-12-11 15:52:51 -06:00
Ross Thompson
6d573b32d2
Changed CPUBusy to Stall in ebu modules.
2022-12-11 15:51:35 -06:00
Ross Thompson
232f866ad1
Renamed CPUBusy to Stall in cache.
2022-12-11 15:49:34 -06:00
Ross Thompson
a58fbd618e
Moved CPUBusy out of HPTW.
2022-12-11 15:48:00 -06:00
Ross Thompson
fbf543bf57
Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
2022-11-29 17:19:31 -06:00
Ross Thompson
b53f8eceef
Renamed Flush to FlushStage in the cache.
2022-11-14 14:11:05 -06:00
Ross Thompson
13e6f7d80b
Changed names of cache signals.
2022-11-13 21:36:12 -06:00
Ross Thompson
9d7ba19fe1
Changed IMWriteDataM to IHWriteDataM.
2022-11-13 12:27:48 -06:00
Ross Thompson
54544ae251
Moved all remaining bus logic from the LSU into ahbcacheinterface.
2022-11-11 14:30:32 -06:00
Ross Thompson
40367eaf45
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-10 15:46:25 -06:00
Ross Thompson
8658a25218
Renamed Word to Beat for ahbcacheinterface.
2022-11-09 17:52:50 -06:00
Ross Thompson
be8e0eee1b
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
David Harris
f7b94c12fc
Moved lsuvirtmem muxes into hptw
2022-11-07 11:13:34 -08:00
Ross Thompson
44171c342d
Reduced complexity of logic supressing cache operations.
2022-11-01 15:23:24 -05:00
Ross Thompson
51408c620e
Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.
2022-10-23 13:46:50 -05:00
Ross Thompson
2c5847b01f
Moving interlockfsm changes to a temporary branch.
...
reduced complexity of cache mux controls.
2022-10-19 15:08:23 -05:00
Ross Thompson
65c2fe294a
Merged cacheable with seluncachedadr.
2022-10-17 13:29:21 -05:00
Ross Thompson
22603464ae
Fixed uncached read bug introduced by yesterday's changes.
2022-10-13 11:11:36 -05:00
Ross Thompson
a4390dd07f
Fixed LSU to correctly handle the difference between LLEN and AHBW.
2022-10-12 12:06:15 -05:00
Ross Thompson
b79872180b
Actually fixed the bus width issue coming out of the cache.
...
The root cause is the ahb bus width can be different from LLEN.
If we switch the d-cache to outputing LLEN and on LLEN intervals, subword read needs to operate on LLEN as well.
Then the cache always outputs LLEN data which may need to be muxed down into 2 or more subwords if ABHW is smaller than LLEN.
2022-10-12 11:33:10 -05:00
Kip Macsai-Goren
1dd9cb6697
quick fix to endianness wapping 64 bit reads in 32 bit confgs
2022-10-11 23:08:02 +00:00
Ross Thompson
7ddcf38fa9
Modified LSU to support DTIM without CSRs.
2022-10-11 14:05:20 -05:00
David Harris
cc9a2fc62d
Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU
2022-10-10 10:22:12 -07:00
David Harris
31e9af0eb2
Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width
2022-10-10 09:10:55 -07:00
Ross Thompson
6ff4abd4f7
Cleaned up the new muxes to select between IROM/ICACHE/BUS and DTIM/DCACHE/BUS.
2022-10-05 15:46:53 -05:00
Ross Thompson
28584e4cca
Fixed wally32e.
2022-10-05 15:37:01 -05:00
Ross Thompson
aa09b1ef16
Fixed bug with combined dtim+bus.
2022-10-05 15:16:01 -05:00
Ross Thompson
98521d073f
Possibly have working dtim + bus config.
2022-10-05 15:08:20 -05:00
