Ross Thompson
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d79c084a70
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Significant refactoring of testbench.
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2023-06-14 17:02:49 -05:00 |
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Ross Thompson
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7ac5239d6a
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Removed old configs from function name module.
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2023-06-14 16:35:55 -05:00 |
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Ross Thompson
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19b7819d53
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Found and fixed the source of the new testbench slow down. I accidentally increased the size of the signature buffer by 10x.
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2023-06-14 14:11:25 -05:00 |
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Ross Thompson
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7fb58f5cac
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more testbench improvements.
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2023-06-14 12:23:26 -05:00 |
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Ross Thompson
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8caa4dfcfb
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Continued improvements to testbench.
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2023-06-14 12:11:55 -05:00 |
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Ross Thompson
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005307fc16
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Resolved the duplicated check signature issue.
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2023-06-14 11:50:12 -05:00 |
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Ross Thompson
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5d0e86f650
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Fixed another issue with the timing of memory resets in the new testbench.
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2023-06-13 16:24:38 -05:00 |
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Ross Thompson
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ed7d785175
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Now have most of the regression tests running again.
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2023-06-13 15:09:40 -05:00 |
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Ross Thompson
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5b0467b287
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Cleaned up testbench more.
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2023-06-13 14:05:17 -05:00 |
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Ross Thompson
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7d53af9206
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Compacted memory resets.
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2023-06-13 13:57:58 -05:00 |
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Ross Thompson
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269d7b2430
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More cleanup.
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2023-06-13 13:54:07 -05:00 |
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Ross Thompson
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40f7031fe7
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Fixed the multliple reads of the same preload memory file.
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2023-06-13 13:52:02 -05:00 |
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Ross Thompson
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261b34af5d
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The testbench now at least runs the arch64i in rv64gc config. Still has several issues
1. need to remove all dead code
2. seems to still be double reading memory files sometimes.
3. batch mode does not work.
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2023-06-13 13:18:46 -05:00 |
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Ross Thompson
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d9f7daf5e0
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The new testbench is almost working except the shadow copy is not working.
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2023-06-12 15:08:23 -05:00 |
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Ross Thompson
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80a6170fe1
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Progress towards new testbench.
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2023-06-12 14:06:17 -05:00 |
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Ross Thompson
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9a1042b0b1
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This parameterizes the testbench but does not use the verilator updates or the new testbench.
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2023-06-12 11:00:30 -05:00 |
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Ross Thompson
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74ccabdf69
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Fixed the garbled output in embench transcript.
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2023-06-08 10:43:46 -05:00 |
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Ross Thompson
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822e60bd3d
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Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem.
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2023-06-05 15:42:05 -05:00 |
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Ross Thompson
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903f2f9063
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Merge branch 'param-lim-merge'
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2023-05-26 16:25:35 -05:00 |
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Ross Thompson
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6509463f3d
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-05-24 13:00:50 -05:00 |
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Ross Thompson
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c5aeb08e5c
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Trying to figure out why the parameterization slowed down modelsim so much.
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2023-05-24 12:44:42 -05:00 |
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Ross Thompson
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485508274e
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Merge pull request #297 from davidharrishmc/dev
Verilator testbench changes
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2023-05-22 13:29:54 -04:00 |
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David Harris
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533ddf5eb3
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Removed force from branch predictor initialization
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2023-05-22 09:57:41 -07:00 |
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David Harris
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f257259045
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Initial testbench cleanup for Verilator
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2023-05-22 09:51:46 -07:00 |
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Ross Thompson
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1dc7fb567b
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Merge branch 'localhistory'
Repair to wave file.
Created implementations of local history. Part of my Ph.D. research.
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2023-05-22 10:13:31 -05:00 |
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David Harris
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d086dbffb4
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Factored FMA tests out of the main 32/64 f/d tests to run in parallel and speed up sim
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2023-05-16 11:37:01 -07:00 |
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Ross Thompson
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e34b25511a
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Baseline localhistory with speculative repair built.
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2023-05-05 15:23:45 -05:00 |
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Ross Thompson
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35a59a1193
|
I think ahead pipelining is working for local history.
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2023-05-03 12:52:32 -05:00 |
|
Limnanthes Serafini
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6fddc591b5
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Finished up testbench reformatting
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2023-04-13 19:18:26 -07:00 |
|
Limnanthes Serafini
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99cd913d75
|
Further indents
|
2023-04-13 19:07:43 -07:00 |
|
Limnanthes Serafini
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0862688168
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testbench code visual improvements
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2023-04-13 19:06:09 -07:00 |
|
Limnanthes Serafini
|
51f6561476
|
A couple indents->spaces
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2023-04-13 17:00:41 -07:00 |
|
Limnanthes Serafini
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ecce9b0ce1
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Fix of InvalDelayed warning
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2023-04-13 16:53:36 -07:00 |
|
Limnanthes Serafini
|
11a5b23bb8
|
Logger significantly improved.
|
2023-04-11 19:29:51 -07:00 |
|
Ross Thompson
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f2c26ff886
|
Merge pull request #206 from AlecVercruysse/coverage2
i$ coverage improvements
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2023-04-05 17:29:35 -05:00 |
|
Alec Vercruysse
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277f507e9a
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add ram1p1rwe for read-only cache ways (remove byte-enable)
- increases coverage
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2023-04-05 11:48:18 -07:00 |
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Limnanthes Serafini
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7de772dcfe
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Merge remote-tracking branch 'upstream/main' into cachesim
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2023-04-05 09:53:05 -07:00 |
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Limnanthes Serafini
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c42d798ff4
|
Commenting, attribution for sim, minor log changes
|
2023-04-05 02:43:02 -07:00 |
|
Limnanthes Serafini
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6abd4ee1b7
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Changed logging enables, debug mode in sim.
|
2023-04-04 23:49:35 -07:00 |
|
Limnanthes Serafini
|
8f3413f0d5
|
CacheSim edits, tests. I/D$ logging, Lim's version
|
2023-04-04 21:12:35 -07:00 |
|
Ross Thompson
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5b188f239b
|
Fixed the d cache logger.
|
2023-04-04 14:19:19 -05:00 |
|
Ross Thompson
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b1a805d1f6
|
Improved d/i cache logger.
|
2023-04-04 13:38:32 -05:00 |
|
David Harris
|
4c41589329
|
Turned off hpm counters
|
2023-03-28 21:28:56 -07:00 |
|
Ross Thompson
|
b4338a5a50
|
Modified the testbench to not use the loggers for unsupported configurations.
|
2023-03-28 16:27:54 -05:00 |
|
Ross Thompson
|
34dd2850e0
|
Disable loggers by default.
|
2023-03-28 16:20:45 -05:00 |
|
Ross Thompson
|
cef75cfe06
|
Now reports if there is a hit or miss.
|
2023-03-28 16:20:14 -05:00 |
|
Ross Thompson
|
a48049f6fe
|
Restored performance counter reports.
|
2023-03-28 16:15:05 -05:00 |
|
Ross Thompson
|
7cc8d4f20c
|
Now have logging of i/d cache addresses, but the performance counter reports are x's.
|
2023-03-28 16:09:54 -05:00 |
|
Ross Thompson
|
108ad671cf
|
Now reports i cache and d cache memory accesses.
|
2023-03-27 23:44:50 -05:00 |
|
Ross Thompson
|
510a0bb3ba
|
First stab at the i cache logger.
|
2023-03-27 18:36:51 -05:00 |
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