Ross Thompson
37078f3d9b
Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.
2023-07-21 13:06:27 -05:00
Ross Thompson
a011b7d591
Merge branch 'testbench-params2'
2023-06-15 15:31:13 -05:00
Ross Thompson
2fc8080102
Got the srams parameterized correctly now.
2023-06-15 13:42:24 -05:00
Ross Thompson
e431f90cf3
Found a whole bunch of files still using the old `define configurations.
2023-06-15 13:09:07 -05:00
Harshini Srinath
1f1fcce062
Update cache.sv
...
Formatting clean up
2023-06-09 08:39:57 -07:00
Ross Thompson
e33db7f9a7
More parameterization. Copied Lim. Still no slow down.
2023-05-24 14:49:22 -05:00
Ross Thompson
a77d403e4c
Merge pull request #233 from AlecVercruysse/coverage3
...
Full I$ coverage
2023-04-14 22:15:11 -05:00
Alec Vercruysse
862d1e0116
replace instances of code duplication for i$ exclusions w/commands
2023-04-14 17:10:39 -07:00
Limnanthes Serafini
5d12afa671
Some cleanup
2023-04-13 21:01:57 -07:00
Alec Vercruysse
800f0245f3
Cachefsm gate LRUWriteEn with ~FlushStage
2023-04-12 13:32:36 -07:00
Alec Vercruysse
e303d99d5b
Merge branch 'main' into coverage3
2023-04-12 09:34:09 -07:00
Alec Vercruysse
214abc7006
Make AdrSelMux and CacheBusAdrMux mux2 if READ_ONLY_CACHE
...
Some address options are only used in the D$ case.
2023-04-12 01:15:35 -07:00
Alec Vercruysse
6dce58125b
Remove FlushStage Logic from CacheLRU
...
For coverage.
LRUWriteEn is gated by FlushStage in cache.sv,
so removing the signal completely avoids future confusion.
Update cache.sv to reflect cacheLRU edit.
2023-04-12 01:15:35 -07:00
Limnanthes Serafini
fdb81e44c9
Minor logic cleanup (will elaborate in PR)
2023-04-11 19:29:39 -07:00
Alec Vercruysse
d3a988c96c
make Cache Flush Logic dependent on !READ_ONLY_CACHE
...
read-only caches do not have flush logic since they do not have to
deal with dirty bits.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
247af17b6b
remove ClearValid from cache
...
The cachefsm hardwired ClearValid logic to zero.
This signal might've been added to potentially add extra functionality
later. Unless that functionality is added, however, it negatively
impacts coverage. If the goal is to maximize coverage, this signal
should be removed and only added when it becomes necessary.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
132074523f
Make entire cache write path conditional on READ_ONLY_CACHE
2023-03-30 10:32:40 -07:00
Alec Vercruysse
dac011c1d2
icache coverage improvements by simplifying logic
2023-03-29 13:04:00 -07:00
Ross Thompson
0511c73e22
Replaced tabs -> spaces cache.
2023-03-24 15:15:38 -05:00
David Harris
471305bda0
Eliminate transitions to FLUSH and WRITEBACK in cachefsm for READ_ONLY_CACHE
2023-03-19 10:41:47 -07:00
Ross Thompson
a27051b8a8
Updated NextAdr to NextSet.
2023-03-13 14:54:13 -05:00
Ross Thompson
cb019f9aed
Updated CAdr to CacheSet.
2023-03-13 14:53:00 -05:00
Ross Thompson
e233b63752
Replaced DCACHE parameter with READ_ONLY_CACHE as the name was confusing in chapter 10.
2023-03-12 13:21:22 -05:00
David Harris
99d179dd3e
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
