4 Commits

Author	SHA1	Message	Date
Ross Thompson	d4398c23fb	Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.	2021-09-16 18:32:29 -05:00
Ross Thompson	4ca0c0ea7d	Added flush controls to cachway.	2021-09-16 16:56:48 -05:00
Ross Thompson	3ff8d0095d	Fixed dcache to prevent latches in FPGA synthesized design.	2021-09-11 12:03:48 -05:00
Ross Thompson	939ff663a5	Forgot to include a few files in the last few commits. ... Also reorganized the dcache by read cpu path, write cpu path, and bus interface path. Changed i/o names on subwordread to match signals in dcache.	2021-08-25 22:30:05 -05:00