Ross Thompson
d2272c0620
Found and fixed the major architecture issue with the mig 7 used in the arty a7 board.
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mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
2023-04-15 11:13:28 -05:00
Ross Thompson
c9445384d7
Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure.
2023-04-14 18:02:16 -05:00
Ross Thompson
b5799c896e
Finally fixed the ddr3 mig script to work correclty.
2023-04-14 11:41:51 -05:00
Ross Thompson
679dc7d73b
Progress on arty a7 board.
2023-04-13 17:57:12 -05:00
Ross Thompson
1861ca8c86
Fixed more bugs in the ila debug constraints.
2023-04-11 14:32:53 -05:00
Ross Thompson
b015e736a0
Updated to help debut Jacob's crossbar woes.
2023-04-11 14:22:42 -05:00
Ross Thompson
c7104bebd3
Fixed sum bugs with arty a7 ila script.
2023-04-11 10:00:06 -05:00
Ross Thompson
6123efd5b2
Updates for arty a7.
2023-04-10 17:02:19 -05:00
Ross Thompson
2abd164d03
Fixed syntax errors in arty7 top level.
2023-04-10 16:08:40 -05:00
Ross Thompson
81fb076e9e
Added more support for Arty A7 board.
2023-04-10 16:01:17 -05:00
Ross Thompson
d2d528cf3c
Finally building ddr3 xilinx ip from script.
2023-04-10 14:36:33 -05:00
Ross Thompson
5aa614858f
Started putting together the arty a7 board package files.
2023-04-10 13:15:55 -05:00
Ross Thompson
b57566e632
Added Jacob's ILA script.
2023-04-06 15:32:36 -05:00
Ross Thompson
c8baffba7c
Started constrains file for arty a7 fpga.
2023-03-24 20:38:13 -05:00
Ross Thompson
c10d98b1c8
Updated fpga constraints to remove critical warning.
2023-03-24 19:09:36 -05:00
Ross Thompson
78ab9f59af
Updated GPIO signal names to reflect book.
2023-03-24 18:55:43 -05:00
Ross Thompson
fe163bbab3
Updated fpga ila script.
2023-03-06 13:14:48 -06:00
Ross Thompson
920bd40822
fpga constraints updates
2023-02-07 15:22:14 -06:00
David Harris
99d179dd3e
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
Ross Thompson
64eaaa670c
More fixes for the debug2.xdc constraints.
2023-01-20 20:48:19 -06:00
Ross Thompson
ee4c78c7fa
More fixes to fpga ila debugger.
2023-01-20 20:28:21 -06:00
Ross Thompson
3effeb42c3
Fixed fpga constraints.
2023-01-20 20:18:04 -06:00
Ross Thompson
442de3f5b7
Updated fpga constraints.
2023-01-20 20:16:33 -06:00
Ross Thompson
a4822c9f54
Added license and comments to new script.
2023-01-20 19:50:33 -06:00
Ross Thompson
b709c224ab
Updated ignore to exclude copied files.
2023-01-20 19:47:33 -06:00
Ross Thompson
e06237ad92
Removed mark_debug vivado directive from source code.
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Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger.
Files output to temporary directory.
2023-01-20 19:43:18 -06:00
Ross Thompson
9d8fed1d35
Test commit.
2023-01-20 17:27:09 -06:00
Ross Thompson
b25b93df11
Repaired fpga debugger.
2023-01-20 15:26:52 -06:00
Ross Thompson
3e1a54e80a
Removed SDC from repo due to copy right issue.
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Modified fpga build flow to reference it outside the repo.
2023-01-20 14:57:06 -06:00
Ross Thompson
6cf5a99b5d
Updated constraints to remove DivBusyE.
2022-12-30 10:51:35 -06:00
Ross Thompson
967d892088
Updated fpga constraints.
2022-12-24 10:21:16 -06:00
Ross Thompson
a2de53aeeb
Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
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Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
2022-12-23 15:10:37 -06:00
Ross Thompson
2cc4d66ded
Renamed IFU and LSU stalls.
2022-12-22 21:56:33 -06:00
Ross Thompson
b7224cc5ba
Updated fpga constraints.
2022-12-21 14:50:01 -06:00
Ross Thompson
e326c9972c
Updated vcu118 piniout.
2022-12-18 14:00:10 -06:00
Ross Thompson
9eac190468
Updated fpga constraints
2022-12-15 16:45:55 -06:00
rachanaerra
4f042b0adb
updated constraints file
2022-12-05 15:05:21 -06:00
Ross Thompson
55335d1db6
Updated top level fpga file.
2022-11-18 11:10:45 -06:00
Ross Thompson
8692bafd04
Updated fpga wave configuration.
2022-11-16 15:57:19 -06:00
Ross Thompson
3de5144ae4
Updated vcu118 constraints to run cpu at 38.43Mhz.
2022-11-15 10:19:38 -06:00
Ross Thompson
b812549f38
Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200 Mhz (2400 MT/s).
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Increased CPU clock speed from 30 Mhz to 35 Mhz.
2022-11-11 15:33:03 -06:00
Ross Thompson
ebfee753ca
Updates to fpga constraints.
2022-11-09 13:52:36 -06:00
Ross Thompson
fd1ef82310
Fixed bug with fpga makefile.
2022-11-07 09:20:05 -06:00
Jacob Pease
ec0cede2f2
Added PLIC signals for debugging on FPGA.
2022-10-25 13:57:09 -05:00
Ross Thompson
1510c2d92f
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
2022-10-24 15:38:39 -05:00
Ross Thompson
ae01c8e824
Forget to include updated xdc file.
2022-10-24 13:51:21 -05:00
Ross Thompson
a45e612008
Updated debug2.xdc for interlock fsm changes.
2022-10-19 17:34:47 -05:00
Ross Thompson
962ba5e4b8
Updated uart settings and fpga wave config.
2022-10-18 15:05:33 -05:00
Ross Thompson
8f18bb9243
Updated constraints file to work with alternate uart.
2022-10-04 17:35:44 -05:00
Ross Thompson
6250a65ede
added new constraints for fpga.
2022-09-17 22:20:06 -05:00
