Ross Thompson
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822e60bd3d
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Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem.
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2023-06-05 15:42:05 -05:00 |
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Ross Thompson
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903f2f9063
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Merge branch 'param-lim-merge'
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2023-05-26 16:25:35 -05:00 |
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Ross Thompson
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6509463f3d
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-05-24 13:00:50 -05:00 |
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Ross Thompson
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c5aeb08e5c
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Trying to figure out why the parameterization slowed down modelsim so much.
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2023-05-24 12:44:42 -05:00 |
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Ross Thompson
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485508274e
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Merge pull request #297 from davidharrishmc/dev
Verilator testbench changes
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2023-05-22 13:29:54 -04:00 |
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David Harris
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533ddf5eb3
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Removed force from branch predictor initialization
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2023-05-22 09:57:41 -07:00 |
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David Harris
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f257259045
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Initial testbench cleanup for Verilator
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2023-05-22 09:51:46 -07:00 |
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Ross Thompson
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1dc7fb567b
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Merge branch 'localhistory'
Repair to wave file.
Created implementations of local history. Part of my Ph.D. research.
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2023-05-22 10:13:31 -05:00 |
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David Harris
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d086dbffb4
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Factored FMA tests out of the main 32/64 f/d tests to run in parallel and speed up sim
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2023-05-16 11:37:01 -07:00 |
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Ross Thompson
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e34b25511a
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Baseline localhistory with speculative repair built.
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2023-05-05 15:23:45 -05:00 |
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Ross Thompson
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35a59a1193
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I think ahead pipelining is working for local history.
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2023-05-03 12:52:32 -05:00 |
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Limnanthes Serafini
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6fddc591b5
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Finished up testbench reformatting
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2023-04-13 19:18:26 -07:00 |
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Limnanthes Serafini
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99cd913d75
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Further indents
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2023-04-13 19:07:43 -07:00 |
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Limnanthes Serafini
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0862688168
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testbench code visual improvements
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2023-04-13 19:06:09 -07:00 |
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Limnanthes Serafini
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51f6561476
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A couple indents->spaces
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2023-04-13 17:00:41 -07:00 |
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Limnanthes Serafini
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ecce9b0ce1
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Fix of InvalDelayed warning
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2023-04-13 16:53:36 -07:00 |
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Limnanthes Serafini
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11a5b23bb8
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Logger significantly improved.
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2023-04-11 19:29:51 -07:00 |
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Ross Thompson
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f2c26ff886
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Merge pull request #206 from AlecVercruysse/coverage2
i$ coverage improvements
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2023-04-05 17:29:35 -05:00 |
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Alec Vercruysse
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277f507e9a
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add ram1p1rwe for read-only cache ways (remove byte-enable)
- increases coverage
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2023-04-05 11:48:18 -07:00 |
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Limnanthes Serafini
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7de772dcfe
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Merge remote-tracking branch 'upstream/main' into cachesim
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2023-04-05 09:53:05 -07:00 |
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Limnanthes Serafini
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c42d798ff4
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Commenting, attribution for sim, minor log changes
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2023-04-05 02:43:02 -07:00 |
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Limnanthes Serafini
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6abd4ee1b7
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Changed logging enables, debug mode in sim.
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2023-04-04 23:49:35 -07:00 |
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Limnanthes Serafini
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8f3413f0d5
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CacheSim edits, tests. I/D$ logging, Lim's version
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2023-04-04 21:12:35 -07:00 |
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Ross Thompson
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5b188f239b
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Fixed the d cache logger.
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2023-04-04 14:19:19 -05:00 |
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Ross Thompson
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b1a805d1f6
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Improved d/i cache logger.
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2023-04-04 13:38:32 -05:00 |
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David Harris
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4c41589329
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Turned off hpm counters
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2023-03-28 21:28:56 -07:00 |
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Ross Thompson
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b4338a5a50
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Modified the testbench to not use the loggers for unsupported configurations.
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2023-03-28 16:27:54 -05:00 |
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Ross Thompson
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34dd2850e0
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Disable loggers by default.
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2023-03-28 16:20:45 -05:00 |
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Ross Thompson
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cef75cfe06
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Now reports if there is a hit or miss.
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2023-03-28 16:20:14 -05:00 |
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Ross Thompson
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a48049f6fe
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Restored performance counter reports.
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2023-03-28 16:15:05 -05:00 |
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Ross Thompson
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7cc8d4f20c
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Now have logging of i/d cache addresses, but the performance counter reports are x's.
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2023-03-28 16:09:54 -05:00 |
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Ross Thompson
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108ad671cf
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Now reports i cache and d cache memory accesses.
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2023-03-27 23:44:50 -05:00 |
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Ross Thompson
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510a0bb3ba
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First stab at the i cache logger.
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2023-03-27 18:36:51 -05:00 |
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Ross Thompson
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78ab9f59af
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Updated GPIO signal names to reflect book.
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2023-03-24 18:55:43 -05:00 |
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David Harris
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3fb9d1fcd0
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Merged bit manip
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2023-03-23 06:55:29 -07:00 |
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David Harris
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c1adc09da0
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Added coverage tests to regression coverage
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2023-03-22 13:00:10 -07:00 |
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Kevin Kim
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07a43e1935
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Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip
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2023-03-20 13:06:10 -07:00 |
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Ross Thompson
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2d49c4582c
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Modified branch logger to indicate when the warmup period is done.
The branch-predictor-simulator also changed to support this.
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2023-03-13 13:26:27 -05:00 |
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Ross Thompson
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ae42150519
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Added script to separate branch.log into separate logs for each benchmark.
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2023-03-12 17:58:36 -05:00 |
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Ross Thompson
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568d0031d2
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Modified the branch log to include markers for the start and end of tests with exclusion of warmup period.
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2023-03-12 17:15:56 -05:00 |
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Ross Thompson
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6d2d7d181e
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Updated testbench to record coremark performance counters.
Added comment about mtval probably not being correct for compressed instructions.
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2023-03-08 17:11:27 -06:00 |
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Kip Macsai-Goren
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1ceaaad592
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Merge remote-tracking branch 'upstream/main' into bit-manip
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2023-03-07 13:45:04 -08:00 |
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Kip Macsai-Goren
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e76e7120c0
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Merge remote-tracking branch 'upstream/main' into bit-manip
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2023-03-04 14:43:12 -08:00 |
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Ross Thompson
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cab6b9dfc8
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Fixed a bunch of odd bugs with the test bench preventing correct measurement of performance counters.
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2023-03-03 17:49:44 -06:00 |
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Ross Thompson
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2d0512936b
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Fixed batch mode regression test to work with hpmc loggic.
Added logic to exclude the embench warmups from preformance counters.
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2023-03-03 14:59:20 -06:00 |
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Ross Thompson
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1c381b0546
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Setup the testbench to exclude the warmup from performance counter reports.
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2023-03-03 13:10:01 -06:00 |
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Ross Thompson
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f6e97cf516
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Added performance new counter prints to testbench.
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2023-03-03 10:42:52 -06:00 |
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Kip Macsai-Goren
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c64723fd5a
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removed comment out on stop in testbench
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2023-02-22 20:47:14 -08:00 |
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Kip Macsai-Goren
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b658329118
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Cleaned up consolidated arch_b tests from tests.vh
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2023-02-22 20:35:01 -08:00 |
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Kip Macsai-Goren
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66833f15f2
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Merge remote-tracking branch 'upstream/main' into main
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2023-02-21 14:48:41 -08:00 |
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